3 files changed, 9 insertions, 58 deletions

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index aeea36a2..8dcc7c5a 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -66,21 +66,12 @@ struct VerilogFrontend : public Frontend {
 		log("        enable support for SystemVerilog assertions and some Yosys extensions\n");
 		log("        replace the implicit -D SYNTHESIS with -D FORMAL\n");
 		log("\n");
-		log("    -noassert\n");
-		log("        ignore assert() statements\n");
-		log("\n");
-		log("    -noassume\n");
-		log("        ignore assume() statements\n");
-		log("\n");
 		log("    -norestrict\n");
-		log("        ignore restrict() statements\n");
+		log("        ignore restrict() assertions\n");
 		log("\n");
 		log("    -assume-asserts\n");
 		log("        treat all assert() statements like assume() statements\n");
 		log("\n");
-		log("    -assert-assumes\n");
-		log("        treat all assume() statements like assert() statements\n");
-		log("\n");
 		log("    -dump_ast1\n");
 		log("        dump abstract syntax tree (before simplification)\n");
 		log("\n");
@@ -238,14 +229,6 @@ struct VerilogFrontend : public Frontend {
 				formal_mode = true;
 				continue;
 			}
-			if (arg == "-noassert") {
-				noassert_mode = true;
-				continue;
-			}
-			if (arg == "-noassume") {
-				noassume_mode = true;
-				continue;
-			}
 			if (arg == "-norestrict") {
 				norestrict_mode = true;
 				continue;
@@ -254,10 +237,6 @@ struct VerilogFrontend : public Frontend {
 				assume_asserts_mode = true;
 				continue;
 			}
-			if (arg == "-assert-assumes") {
-				assert_assumes_mode = true;
-				continue;
-			}
 			if (arg == "-dump_ast1") {
 				flag_dump_ast1 = true;
 				continue;
diff --git a/frontends/verilog/verilog_frontend.h b/frontends/verilog/verilog_frontend.h
index 523bbc89..16edc798 100644
--- a/frontends/verilog/verilog_frontend.h
+++ b/frontends/verilog/verilog_frontend.h
@@ -54,21 +54,12 @@ namespace VERILOG_FRONTEND
 	// running in -formal mode
 	extern bool formal_mode;
 
-	// running in -noassert mode
-	extern bool noassert_mode;
-
-	// running in -noassume mode
-	extern bool noassume_mode;
-
 	// running in -norestrict mode
 	extern bool norestrict_mode;
 
 	// running in -assume-asserts mode
 	extern bool assume_asserts_mode;
 
-	// running in -assert-assumes mode
-	extern bool assert_assumes_mode;
-
 	// running in -lib mode
 	extern bool lib_mode;
 
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 16cac146..2389d7d3 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -58,8 +58,7 @@ namespace VERILOG_FRONTEND {
 	bool do_not_require_port_stubs;
 	bool default_nettype_wire;
 	bool sv_mode, formal_mode, lib_mode;
-	bool noassert_mode, noassume_mode, norestrict_mode;
-	bool assume_asserts_mode, assert_assumes_mode;
+	bool norestrict_mode, assume_asserts_mode;
 	bool current_wire_rand, current_wire_const;
 	std::istream *lexin;
 }
@@ -882,15 +881,9 @@ param_decl_list:
 
 single_param_decl:
 	TOK_ID '=' expr {
-		AstNode *node;
-		if (astbuf1 == nullptr) {
-			if (!sv_mode)
-				frontend_verilog_yyerror("syntax error");
-			node = new AstNode(AST_PARAMETER);
-			node->children.push_back(AstNode::mkconst_int(0, true));
-		} else {
-			node = astbuf1->clone();
-		}
+		if (astbuf1 == nullptr)
+			frontend_verilog_yyerror("syntax error");
+		AstNode *node = astbuf1->clone();
 		node->str = *$1;
 		delete node->children[0];
 		node->children[0] = $3;
@@ -1282,28 +1275,16 @@ opt_stmt_label:
 
 assert:
 	opt_stmt_label TOK_ASSERT opt_property '(' expr ')' ';' {
-		if (noassert_mode)
-			delete $5;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_ASSUME : AST_ASSERT, $5));
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' expr ')' ';' {
-		if (noassume_mode)
-			delete $5;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_ASSERT : AST_ASSUME, $5));
+		ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
 	} |
 	opt_stmt_label TOK_ASSERT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (noassert_mode)
-			delete $6;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
+		ast_stack.back()->children.push_back(new AstNode(assume_asserts_mode ? AST_FAIR : AST_LIVE, $6));
 	} |
 	opt_stmt_label TOK_ASSUME opt_property '(' TOK_EVENTUALLY expr ')' ';' {
-		if (noassume_mode)
-			delete $6;
-		else
-			ast_stack.back()->children.push_back(new AstNode(assert_assumes_mode ? AST_LIVE : AST_FAIR, $6));
+		ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
 	} |
 	opt_stmt_label TOK_COVER opt_property '(' expr ')' ';' {
 		ast_stack.back()->children.push_back(new AstNode(AST_COVER, $5));