5 files changed, 16 insertions, 16 deletions
diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h
index 44315d49..b5349db5 100644
--- a/frontends/ast/ast.h
+++ b/frontends/ast/ast.h
@@ -269,7 +269,7 @@ namespace AST
 	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
-	// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
+	// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
 	struct AstModule : RTLIL::Module {
 		AstNode *ast;
 		bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 4ed0e2ba..a2655e9a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -176,13 +176,13 @@ struct AST_INTERNAL::ProcessGenerator
 	RTLIL::Process *proc;
 	RTLIL::SigSpec outputSignals;
 
-	// This always points to the RTLIL::CaseRule beeing filled at the moment
+	// This always points to the RTLIL::CaseRule being filled at the moment
 	RTLIL::CaseRule *current_case;
 
 	// This map contains the replacement pattern to be used in the right hand side
 	// of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
 	// hand side of the 2nd assignment needs to be replace with the temporary signal holding
-	// the value assigned in the first assignment. So when the first assignement is processed
+	// the value assigned in the first assignment. So when the first assignment is processed
 	// the according information is appended to subst_rvalue_from and subst_rvalue_to.
 	stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
 
@@ -192,7 +192,7 @@ struct AST_INTERNAL::ProcessGenerator
 	// signal that is used as input for the register that drives the signal foo.
 	stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
 
-	// The code here generates a number of temprorary signal for each output register. This
+	// The code here generates a number of temporary signal for each output register. This
 	// map helps generating nice numbered names for all this temporary signals.
 	std::map<RTLIL::Wire*, int> new_temp_count;
 
@@ -766,7 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	// in the following big switch() statement there are some uses of
 	// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
 	// cases this variable is used to hold the type of the cell that should
-	// be instanciated for this type of AST node.
+	// be instantiated for this type of AST node.
 	std::string type_name;
 
 	current_filename = filename;
@@ -775,7 +775,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 	switch (type)
 	{
 	// simply ignore this nodes.
-	// they are eighter leftovers from simplify() or are referenced by other nodes
+	// they are either leftovers from simplify() or are referenced by other nodes
 	// and are only accessed here thru this references
 	case AST_TASK:
 	case AST_FUNCTION:
@@ -1073,7 +1073,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 		}
 
 	// generate cells for unary operations: $reduce_bool
-	// (this is actually just an $reduce_or, but for clearity a different cell type is used)
+	// (this is actually just an $reduce_or, but for clarity a different cell type is used)
 	if (0) { case AST_REDUCE_BOOL:  type_name = "$reduce_bool"; }
 		{
 			RTLIL::SigSpec arg = children[0]->genRTLIL();
@@ -1415,7 +1415,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 }
 
 // this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
-// signals must be substituted before beeing used as input values (used by ProcessGenerator)
+// signals must be substituted before being used as input values (used by ProcessGenerator)
 // note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
 RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
 {
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 29935652..cc9bbd23 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -41,7 +41,7 @@ YOSYS_NAMESPACE_BEGIN
 using namespace AST;
 using namespace AST_INTERNAL;
 
-// convert the AST into a simpler AST that has all parameters subsitited by their
+// convert the AST into a simpler AST that has all parameters substituted by their
 // values, unrolled for-loops, expanded generate blocks, etc. when this function
 // is done with an AST it can be converted into RTLIL using genRTLIL().
 //
@@ -167,13 +167,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	set_line_num(linenum);
 
 	// we do not look inside a task or function
-	// (but as soon as a task of function is instanciated we process the generated AST as usual)
+	// (but as soon as a task or function is instantiated we process the generated AST as usual)
 	if (type == AST_FUNCTION || type == AST_TASK) {
 		recursion_counter--;
 		return false;
 	}
 
-	// deactivate all calls to non-synthesis system taks
+	// deactivate all calls to non-synthesis system tasks
 	if ((type == AST_FCALL || type == AST_TCALL) && (str == "$display" || str == "$strobe" || str == "$monitor" || str == "$time" || str == "$stop" || str == "$finish" ||
 			str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
 		log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum);
@@ -1085,7 +1085,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 		goto apply_newNode;
 	}
 
-	// replace primitives with assignmens
+	// replace primitives with assignments
 	if (type == AST_PRIMITIVE)
 	{
 		if (children.size() < 2)
@@ -2260,7 +2260,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
 		name_map.swap(backup_name_map);
 }
 
-// rename stuff (used when tasks of functions are instanciated)
+// rename stuff (used when tasks of functions are instantiated)
 void AstNode::replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules)
 {
 	if (type == AST_BLOCK)
@@ -2588,7 +2588,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
 	return did_something;
 }
 
-// calulate memory dimensions
+// calculate memory dimensions
 void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
 {
 	log_assert(type == AST_MEMORY);
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index ce975358..897a7f32 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -789,7 +789,7 @@ struct VerificPass : public Pass {
 		log("\n");
 		log("    verific -import [-gates] {-all | <top-module>..}\n");
 		log("\n");
-		log("Elaborate the design for the sepcified top modules, import to Yosys and\n");
+		log("Elaborate the design for the specified top modules, import to Yosys and\n");
 		log("reset the internal state of Verific. A gate-level netlist is created\n");
 		log("when called with -gates.\n");
 		log("\n");
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 817109b7..74b8a870 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -340,7 +340,7 @@ struct VerilogDefaults : public Pass {
 		log("\n");
 		log("    verilog_defaults -add [options]\n");
 		log("\n");
-		log("Add the sepcified options to the list of default options to read_verilog.\n");
+		log("Add the specified options to the list of default options to read_verilog.\n");
 		log("\n");
 		log("\n");
 		log("    verilog_defaults -clear");