diff options
Diffstat (limited to 'frontends')
| -rw-r--r-- | frontends/ast/ast.cc | 38 | ||||
| -rw-r--r-- | frontends/ast/ast.h | 6 | ||||
| -rw-r--r-- | frontends/ast/genrtlil.cc | 10 | ||||
| -rw-r--r-- | frontends/ilang/lexer.l | 1 | ||||
| -rw-r--r-- | frontends/ilang/parser.y | 5 |
5 files changed, 4 insertions, 56 deletions
diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 6423cae2..ffbcf314 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -876,44 +876,6 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin return modname; } -// recompile a module from AST with updated widths for auto-wires -// (auto-wires are wires that are used but not declared an thus have an automatically determined width) -void AstModule::update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes) -{ - log_header("Executing AST frontend in update_auto_wires mode using pre-parsed AST for module `%s'.\n", name.c_str()); - - current_ast = NULL; - flag_dump_ast1 = false; - flag_dump_ast2 = false; - flag_dump_vlog = false; - flag_nolatches = nolatches; - flag_nomem2reg = nomem2reg; - flag_mem2reg = mem2reg; - flag_lib = lib; - flag_noopt = noopt; - use_internal_line_num(); - - for (auto it = auto_sizes.begin(); it != auto_sizes.end(); it++) { - log("Adding extra wire declaration to AST: wire [%d:0] %s\n", it->second - 1, it->first.c_str()); - AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, AstNode::mkconst_int(it->second - 1, true), AstNode::mkconst_int(0, true))); - wire->str = it->first; - ast->children.insert(ast->children.begin(), wire); - } - - AstModule *newmod = process_module(ast); - - delete ast; - ast = newmod->ast; - newmod->ast = NULL; - - wires.swap(newmod->wires); - cells.swap(newmod->cells); - processes.swap(newmod->processes); - connections.swap(newmod->connections); - attributes.swap(newmod->attributes); - delete newmod; -} - RTLIL::Module *AstModule::clone() const { AstModule *new_mod = new AstModule; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index f9f47f6a..34983225 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -228,7 +228,6 @@ namespace AST bool nolatches, nomem2reg, mem2reg, lib, noopt; virtual ~AstModule(); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters, std::set<RTLIL::IdString> signed_parameters); - virtual void update_auto_wires(std::map<RTLIL::IdString, int> auto_sizes); virtual RTLIL::Module *clone() const; }; @@ -239,9 +238,8 @@ namespace AST extern void (*set_line_num)(int); extern int (*get_line_num)(); - // set set_line_num and get_line_num to internal dummy functions - // (done by simplify(), AstModule::derive and AstModule::update_auto_wires to control - // the filename and linenum properties of new nodes not generated by a frontend parser) + // set set_line_num and get_line_num to internal dummy functions (done by simplify() and AstModule::derive + // to control the filename and linenum properties of new nodes not generated by a frontend parser) void use_internal_line_num(); } diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 177c1ec5..66b670c7 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -917,15 +917,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) RTLIL::Wire *wire = new RTLIL::Wire; wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum); wire->name = str; - if (width_hint >= 0) { - wire->width = width_hint; - log("Warning: Identifier `%s' is implicitly declared with width %d at %s:%d.\n", - str.c_str(), width_hint, filename.c_str(), linenum); - } else { - log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", - str.c_str(), filename.c_str(), linenum); - } - wire->auto_width = true; + log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum); current_module->wires[str] = wire; } else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) { diff --git a/frontends/ilang/lexer.l b/frontends/ilang/lexer.l index 73bc894b..287f9dbf 100644 --- a/frontends/ilang/lexer.l +++ b/frontends/ilang/lexer.l @@ -41,7 +41,6 @@ "parameter" { return TOK_PARAMETER; } "wire" { return TOK_WIRE; } "memory" { return TOK_MEMORY; } -"auto" { return TOK_AUTO; } "width" { return TOK_WIDTH; } "offset" { return TOK_OFFSET; } "size" { return TOK_SIZE; } diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y index dc39cf93..71c63bc4 100644 --- a/frontends/ilang/parser.y +++ b/frontends/ilang/parser.y @@ -54,7 +54,7 @@ using namespace ILANG_FRONTEND; %token TOK_CELL TOK_CONNECT TOK_SWITCH TOK_CASE TOK_ASSIGN TOK_SYNC %token TOK_LOW TOK_HIGH TOK_POSEDGE TOK_NEGEDGE TOK_EDGE TOK_ALWAYS TOK_INIT %token TOK_UPDATE TOK_PROCESS TOK_END TOK_INVALID TOK_EOL TOK_OFFSET -%token TOK_PARAMETER TOK_ATTRIBUTE TOK_AUTO TOK_MEMORY TOK_SIZE +%token TOK_PARAMETER TOK_ATTRIBUTE TOK_MEMORY TOK_SIZE %type <sigspec> sigspec sigspec_list %type <integer> sync_type @@ -124,9 +124,6 @@ wire_stmt: }; wire_options: - wire_options TOK_AUTO { - current_wire->auto_width = true; - } | wire_options TOK_WIDTH TOK_INT { current_wire->width = $3; } | |