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-rw-r--r--kernel/rtlil.cc20
1 files changed, 20 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index bd7f5c9f..560ef4b6 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -996,6 +996,14 @@ namespace {
return;
}
+ if (cell->type == "$tribuf") {
+ port("\\A", param("\\WIDTH"));
+ port("\\Y", param("\\WIDTH"));
+ port("\\EN", 1);
+ check_expected();
+ return;
+ }
+
if (cell->type == "$assert") {
port("\\A", 1);
port("\\EN", 1);
@@ -1032,6 +1040,8 @@ namespace {
if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
+ if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
+
if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
@@ -1740,6 +1750,16 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
return cell;
}
+RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y)
+{
+ RTLIL::Cell *cell = addCell(name, "$tribuf");
+ cell->parameters["\\WIDTH"] = sig_a.size();
+ cell->setPort("\\A", sig_a);
+ cell->setPort("\\EN", sig_en);
+ cell->setPort("\\Y", sig_y);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
{
RTLIL::Cell *cell = addCell(name, "$assert");