diff options
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/celltypes.h | 14 | ||||
| -rw-r--r-- | kernel/driver.cc | 6 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 18 | ||||
| -rw-r--r-- | kernel/rtlil.h | 2 |
4 files changed, 20 insertions, 20 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index d3c848f4..20d68d55 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -171,7 +171,7 @@ struct CellTypes if (cell_types.count(type) > 0) return true; for (auto design : designs) - if (design->modules.count(type) > 0) + if (design->modules_.count(type) > 0) return true; return false; } @@ -180,9 +180,9 @@ struct CellTypes { if (cell_types.count(type) == 0) { for (auto design : designs) - if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires_.count(port)) - return design->modules.at(type)->wires_.at(port)->port_output; + if (design->modules_.count(type) > 0) { + if (design->modules_.at(type)->wires_.count(port)) + return design->modules_.at(type)->wires_.at(port)->port_output; return false; } return false; @@ -203,9 +203,9 @@ struct CellTypes { if (cell_types.count(type) == 0) { for (auto design : designs) - if (design->modules.count(type) > 0) { - if (design->modules.at(type)->wires_.count(port)) - return design->modules.at(type)->wires_.at(port)->port_input; + if (design->modules_.count(type) > 0) { + if (design->modules_.at(type)->wires_.count(port)) + return design->modules_.at(type)->wires_.at(port)->port_input; return false; } return false; diff --git a/kernel/driver.cc b/kernel/driver.cc index edf23cd2..7a1c7ed1 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -234,14 +234,14 @@ static char *readline_obj_generator(const char *text, int state) if (design->selected_active_module.empty()) { - for (auto &it : design->modules) + for (auto &it : design->modules_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) obj_names.push_back(strdup(RTLIL::id2cstr(it.first.c_str()))); } else - if (design->modules.count(design->selected_active_module) > 0) + if (design->modules_.count(design->selected_active_module) > 0) { - RTLIL::Module *module = design->modules.at(design->selected_active_module); + RTLIL::Module *module = design->modules_.at(design->selected_active_module); for (auto &it : module->wires_) if (RTLIL::unescape_id(it.first).substr(0, len) == text) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5fdcb025..5709875e 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -175,7 +175,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) del_list.clear(); for (auto mod_name : selected_modules) { - if (design->modules.count(mod_name) == 0) + if (design->modules_.count(mod_name) == 0) del_list.push_back(mod_name); selected_members.erase(mod_name); } @@ -184,7 +184,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) del_list.clear(); for (auto &it : selected_members) - if (design->modules.count(it.first) == 0) + if (design->modules_.count(it.first) == 0) del_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -192,7 +192,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) { del_list.clear(); for (auto memb_name : it.second) - if (design->modules[it.first]->count_id(memb_name) == 0) + if (design->modules_[it.first]->count_id(memb_name) == 0) del_list.push_back(memb_name); for (auto memb_name : del_list) it.second.erase(memb_name); @@ -203,8 +203,8 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) for (auto &it : selected_members) if (it.second.size() == 0) del_list.push_back(it.first); - else if (it.second.size() == design->modules[it.first]->wires_.size() + design->modules[it.first]->memories.size() + - design->modules[it.first]->cells_.size() + design->modules[it.first]->processes.size()) + else if (it.second.size() == design->modules_[it.first]->wires_.size() + design->modules_[it.first]->memories.size() + + design->modules_[it.first]->cells_.size() + design->modules_[it.first]->processes.size()) add_list.push_back(it.first); for (auto mod_name : del_list) selected_members.erase(mod_name); @@ -213,7 +213,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) selected_modules.insert(mod_name); } - if (selected_modules.size() == design->modules.size()) { + if (selected_modules.size() == design->modules_.size()) { full_selection = true; selected_modules.clear(); selected_members.clear(); @@ -222,14 +222,14 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) RTLIL::Design::~Design() { - for (auto it = modules.begin(); it != modules.end(); it++) + for (auto it = modules_.begin(); it != modules_.end(); it++) delete it->second; } void RTLIL::Design::check() { #ifndef NDEBUG - for (auto &it : modules) { + for (auto &it : modules_) { assert(it.first == it.second->name); assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$')); it.second->check(); @@ -239,7 +239,7 @@ void RTLIL::Design::check() void RTLIL::Design::optimize() { - for (auto &it : modules) + for (auto &it : modules_) it.second->optimize(); for (auto &it : selection_stack) it.optimize(this); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 2fbfe804..7249f0ca 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -340,7 +340,7 @@ struct RTLIL::Selection struct RTLIL::Design { - std::map<RTLIL::IdString, RTLIL::Module*> modules; + std::map<RTLIL::IdString, RTLIL::Module*> modules_; std::vector<RTLIL::Selection> selection_stack; std::map<RTLIL::IdString, RTLIL::Selection> selection_vars; |