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-rw-r--r--kernel/celltypes.h3
-rw-r--r--kernel/consteval.h7
-rw-r--r--kernel/rtlil.cc7
-rw-r--r--kernel/rtlil.h6
-rw-r--r--kernel/satgen.h10
5 files changed, 9 insertions, 24 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 99386382..23d06f82 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -98,7 +98,6 @@ struct CellTypes
cell_types.insert("$pmux");
cell_types.insert("$slice");
cell_types.insert("$concat");
- cell_types.insert("$safe_pmux");
cell_types.insert("$lut");
cell_types.insert("$assert");
}
@@ -307,7 +306,7 @@ struct CellTypes
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &sel)
{
- if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_") {
+ if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_") {
RTLIL::Const ret = arg1;
for (size_t i = 0; i < sel.bits.size(); i++)
if (sel.bits[i] == RTLIL::State::S1) {
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 529d8962..dbe13ea7 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -104,7 +104,7 @@ struct ConstEval
if (cell->hasPort("\\B"))
sig_b = cell->getPort("\\B");
- if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux" || cell->type == "$_MUX_")
+ if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$_MUX_")
{
std::vector<RTLIL::SigSpec> y_candidates;
int count_maybe_set_s_bits = 0;
@@ -125,10 +125,7 @@ struct ConstEval
count_set_s_bits++;
}
- if (cell->type == "$safe_pmux" && count_set_s_bits > 1)
- y_candidates.clear();
-
- if ((cell->type == "$safe_pmux" && count_maybe_set_s_bits > 1) || count_set_s_bits == 0)
+ if (count_set_s_bits == 0)
y_candidates.push_back(sig_a);
std::vector<RTLIL::Const> y_values;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 8ff56451..201c717e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -608,7 +608,7 @@ namespace {
return;
}
- if (cell->type == "$pmux" || cell->type == "$safe_pmux") {
+ if (cell->type == "$pmux") {
port("\\A", param("\\WIDTH"));
port("\\B", param("\\WIDTH") * param("\\S_WIDTH"));
port("\\S", param("\\S_WIDTH"));
@@ -1293,7 +1293,6 @@ DEF_METHOD(LogicOr, 1, "$logic_or")
}
DEF_METHOD(Mux, "$mux", 0)
DEF_METHOD(Pmux, "$pmux", 1)
-DEF_METHOD(SafePmux, "$safe_pmux", 1)
#undef DEF_METHOD
#define DEF_METHOD_2(_func, _type, _P1, _P2) \
@@ -1637,10 +1636,10 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
return;
- if (type == "$mux" || type == "$pmux" || type == "$safe_pmux")
+ if (type == "$mux" || type == "$pmux")
{
parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
- if (type == "$pmux" || type == "$safe_pmux")
+ if (type == "$pmux")
parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
check();
return;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 1e967f26..10da7463 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -662,9 +662,8 @@ public:
RTLIL::Cell* addLogicAnd (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
RTLIL::Cell* addLogicOr (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, bool is_signed = false);
- RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
- RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
- RTLIL::Cell* addSafePmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
+ RTLIL::Cell* addMux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
+ RTLIL::Cell* addPmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s, RTLIL::SigSpec sig_y);
RTLIL::Cell* addSlice (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset);
RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
@@ -743,7 +742,6 @@ public:
RTLIL::SigSpec Mux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s);
RTLIL::SigSpec Pmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s);
- RTLIL::SigSpec SafePmux (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_s);
RTLIL::SigSpec InvGate (RTLIL::IdString name, RTLIL::SigSpec sig_a);
RTLIL::SigSpec AndGate (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 1ada1e16..8284cdeb 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -316,7 +316,7 @@ struct SatGen
return true;
}
- if (cell->type == "$pmux" || cell->type == "$safe_pmux")
+ if (cell->type == "$pmux")
{
std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort("\\B"), timestep);
@@ -330,8 +330,6 @@ struct SatGen
std::vector<int> part_of_b(b.begin()+i*a.size(), b.begin()+(i+1)*a.size());
tmp = ez->vec_ite(s.at(i), part_of_b, tmp);
}
- if (cell->type == "$safe_pmux")
- tmp = ez->vec_ite(ez->onehot(s, true), tmp, a);
ez->assume(ez->vec_eq(tmp, yy));
if (model_undef)
@@ -370,12 +368,6 @@ struct SatGen
int maybe_a = ez->NOT(maybe_one_hot);
- if (cell->type == "$safe_pmux") {
- maybe_a = ez->OR(maybe_a, maybe_many_hot);
- bits_set = ez->vec_ite(sure_many_hot, ez->vec_or(a, undef_a), bits_set);
- bits_clr = ez->vec_ite(sure_many_hot, ez->vec_or(ez->vec_not(a), undef_a), bits_clr);
- }
-
bits_set = ez->vec_ite(maybe_a, ez->vec_or(bits_set, ez->vec_or(bits_set, ez->vec_or(a, undef_a))), bits_set);
bits_clr = ez->vec_ite(maybe_a, ez->vec_or(bits_clr, ez->vec_or(bits_clr, ez->vec_or(ez->vec_not(a), undef_a))), bits_clr);