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Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
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1 files changed, 12 insertions, 0 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 09be0870..b84e1b30 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -97,6 +97,12 @@ The width of the output port \B{Y}. Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators. +The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always +extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments +with {\tt x}-bits if the most significant bit is {\tt x}.) This is used +internally to correctly implement the {\tt ==} and {\tt !=} operators for +constant arguments. + \subsection{Multiplexers} Multiplexers are generated by the Verilog HDL frontend for {\tt @@ -147,6 +153,9 @@ Verilog & Cell Type \\ \hline \lstinline[language=Verilog]; Y = A && B; & {\tt \$logic\_and} \\ \lstinline[language=Verilog]; Y = A || B; & {\tt \$logic\_or} \\ +\hline +\lstinline[language=Verilog]; Y = A === B; & {\tt \$eqx} \\ +\lstinline[language=Verilog]; Y = A !== B; & {\tt \$nex} \\ \end{tabular} \hfil \begin{tabular}[t]{ll} @@ -263,6 +272,9 @@ the \B{CLK} input is not used. \item \B{CLK\_POLARITY} \\ Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative edge if this parameter is {\tt 1'b0}. + +\item \B{PRIORITY} \\ +The cell with the higher integer value in this parameter wins a write conflict. \end{itemize} The HDL frontend models a memory using RTLIL::Memory objects and asynchronous |