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@@ -97,12 +97,6 @@ The width of the output port \B{Y}.
Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators.
-The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always
-extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments
-with {\tt x}-bits if the most significant bit is {\tt x}.) This is used
-internally to correctly implement the {\tt ==} and {\tt !=} operators for
-constant arguments.
-
\subsection{Multiplexers}
Multiplexers are generated by the Verilog HDL frontend for {\tt