1 files changed, 3 insertions, 3 deletions
diff --git a/manual/CHAPTER_Intro.tex b/manual/CHAPTER_Intro.tex
index f735d46b..76e5d847 100644
--- a/manual/CHAPTER_Intro.tex
+++ b/manual/CHAPTER_Intro.tex
@@ -35,7 +35,7 @@ The proposed custom HDL synthesis tool should be licensed under a Free
 and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL
 synthesis tool would have been needed as basis to build upon. The main advantages
 of choosing Verilog or VHDL is the ability to synthesize existing HDL code and
-to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool, 
+to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool,
 such a tool would have to provide a feature-complete implementation of the
 synthesizable HDL subset.
 
@@ -68,7 +68,7 @@ problem of implementing a HDL synthesis tool is approached in the case of
 Yosys.
 
 Chapter~\ref{chapter:overview} contains a more detailed overview of the
-implementation of Yosys. This chapter covers the data structures used in 
+implementation of Yosys. This chapter covers the data structures used in
 Yosys to represent a design in detail and is therefore recommended reading
 for everyone who is interested in understanding the Yosys internals.
 
@@ -81,7 +81,7 @@ is recommended reading for everyone who actually wants to read or write
 Yosys source code. The chapter concludes with an example loadable module
 for Yosys.
 
-Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} 
+Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap}
 cover three important pieces of the synthesis pipeline: The Verilog frontend,
 the optimization passes and the technology mapping to the target architecture,
 respectively.