path: root/manual/CHAPTER_Techmap.tex
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Diffstat (limited to 'manual/CHAPTER_Techmap.tex')
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex
index 6a84864e..be74c356 100644
--- a/manual/CHAPTER_Techmap.tex
+++ b/manual/CHAPTER_Techmap.tex
@@ -27,7 +27,7 @@ cells with the provided implementation.
When no map file is provided, {\tt techmap} uses a built-in map file that
maps the Yosys RTL cell types to the internal gate library used by Yosys.
-The curious reader may find this map file as {\tt techlibs/stdcells.v} in
+The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in
the Yosys source tree.
Additional features have been added to {\tt techmap} to allow for conditional