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-rw-r--r--manual/PRESENTATION_ExAdv/.gitignore1
-rw-r--r--manual/PRESENTATION_ExAdv/Makefile6
-rw-r--r--manual/PRESENTATION_ExAdv/select_01.v15
-rw-r--r--manual/PRESENTATION_ExAdv/select_01.ys10
4 files changed, 32 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExAdv/.gitignore b/manual/PRESENTATION_ExAdv/.gitignore
new file mode 100644
index 00000000..cf658897
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/.gitignore
@@ -0,0 +1 @@
+*.dot
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
new file mode 100644
index 00000000..f38bd6ce
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -0,0 +1,6 @@
+
+all: select_01.pdf
+
+select_01.pdf: select_01.v select_01.ys
+ ../../yosys select_01.ys
+
diff --git a/manual/PRESENTATION_ExAdv/select_01.v b/manual/PRESENTATION_ExAdv/select_01.v
new file mode 100644
index 00000000..1b0bb7ee
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select_01.v
@@ -0,0 +1,15 @@
+module test(clk, s, a, y);
+ input clk, s;
+ input [15:0] a;
+ output [15:0] y;
+ reg [15:0] b, c;
+
+ always @(posedge clk) begin
+ b <= a;
+ c <= b;
+ end
+
+ wire [15:0] state_a = (a ^ b) + c;
+ wire [15:0] state_b = (a ^ b) - c;
+ assign y = !s ? state_a : state_b;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select_01.ys b/manual/PRESENTATION_ExAdv/select_01.ys
new file mode 100644
index 00000000..a7fe2728
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/select_01.ys
@@ -0,0 +1,10 @@
+read_verilog select_01.v
+hierarchy -check -top test
+proc; opt
+cd test
+select -set cone_a state_a %ci*:-$dff
+select -set cone_b state_b %ci*:-$dff
+select -set cone_ab @cone_a @cone_b %i
+show -prefix select_01 -format pdf -notitle \
+ -color red @cone_ab -color magenta @cone_a \
+ -color blue @cone_b