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-rw-r--r--manual/PRESENTATION_ExAdv/Makefile10
-rw-r--r--manual/PRESENTATION_ExAdv/macc_simple_test.v6
-rw-r--r--manual/PRESENTATION_ExAdv/macc_simple_test.ys36
-rw-r--r--manual/PRESENTATION_ExAdv/macc_simple_test_01.v6
-rw-r--r--manual/PRESENTATION_ExAdv/macc_simple_test_02.v6
-rw-r--r--manual/PRESENTATION_ExAdv/macc_simple_xmap.v6
-rw-r--r--manual/PRESENTATION_ExAdv/select.v (renamed from manual/PRESENTATION_ExAdv/select_01.v)0
-rw-r--r--manual/PRESENTATION_ExAdv/select.ys (renamed from manual/PRESENTATION_ExAdv/select_01.ys)4
8 files changed, 69 insertions, 5 deletions
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index 2a2858e5..60da3169 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,8 +1,9 @@
-all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
+all: select.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf \
+ macc_simple_xmap.pdf
-select_01.pdf: select_01.v select_01.ys
- ../../yosys select_01.ys
+select.pdf: select.v select.ys
+ ../../yosys select.ys
red_or3x1.pdf: red_or3x1_*
../../yosys red_or3x1_test.ys
@@ -19,3 +20,6 @@ mulshift.pdf: mulshift_*
addshift.pdf: addshift_*
../../yosys addshift_test.ys
+macc_simple_xmap.pdf: macc_simple_*.v macc_simple_test.ys
+ ../../yosys macc_simple_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.v b/manual/PRESENTATION_ExAdv/macc_simple_test.v
new file mode 100644
index 00000000..6358a47c
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, y);
+input [15:0] a, b;
+input [31:0] c, d;
+output [31:0] y;
+assign y = a * b + c + d;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test.ys b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
new file mode 100644
index 00000000..d5b01237
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test.ys
@@ -0,0 +1,36 @@
+read_verilog macc_simple_test.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_00a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -constports -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_00b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+read_verilog macc_simple_test_01.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_01a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_01b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_test_02.v
+hierarchy -check -top test;;
+
+show -prefix macc_simple_test_02a -format pdf -notitle -lib macc_simple_xmap.v
+
+extract -map macc_simple_xmap.v;;
+show -prefix macc_simple_test_02b -format pdf -notitle -lib macc_simple_xmap.v
+
+#################################################
+
+design -reset
+read_verilog macc_simple_xmap.v
+hierarchy -check -top macc_16_16_32;;
+
+show -prefix macc_simple_xmap -format pdf -notitle
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_01.v b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
new file mode 100644
index 00000000..8391fb38
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test_01.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + c*d + x;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_test_02.v b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
new file mode 100644
index 00000000..3630102f
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_test_02.v
@@ -0,0 +1,6 @@
+module test(a, b, c, d, x, y);
+input [15:0] a, b, c, d;
+input [31:0] x;
+output [31:0] y;
+assign y = a*b + (c*d + x);
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/macc_simple_xmap.v b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
new file mode 100644
index 00000000..42f5bae9
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/macc_simple_xmap.v
@@ -0,0 +1,6 @@
+module macc_16_16_32(a, b, c, y);
+input [15:0] a, b;
+input [31:0] c;
+output [31:0] y;
+assign y = a*b + c;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/select_01.v b/manual/PRESENTATION_ExAdv/select.v
index 1b0bb7ee..1b0bb7ee 100644
--- a/manual/PRESENTATION_ExAdv/select_01.v
+++ b/manual/PRESENTATION_ExAdv/select.v
diff --git a/manual/PRESENTATION_ExAdv/select_01.ys b/manual/PRESENTATION_ExAdv/select.ys
index a7fe2728..9832c104 100644
--- a/manual/PRESENTATION_ExAdv/select_01.ys
+++ b/manual/PRESENTATION_ExAdv/select.ys
@@ -1,10 +1,10 @@
-read_verilog select_01.v
+read_verilog select.v
hierarchy -check -top test
proc; opt
cd test
select -set cone_a state_a %ci*:-$dff
select -set cone_b state_b %ci*:-$dff
select -set cone_ab @cone_a @cone_b %i
-show -prefix select_01 -format pdf -notitle \
+show -prefix select -format pdf -notitle \
-color red @cone_ab -color magenta @cone_a \
-color blue @cone_b