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-rw-r--r--manual/PRESENTATION_ExAdv/Makefile5
-rw-r--r--manual/PRESENTATION_ExAdv/red_or3x1_cells.v5
-rw-r--r--manual/PRESENTATION_ExAdv/red_or3x1_map.v48
-rw-r--r--manual/PRESENTATION_ExAdv/red_or3x1_test.v5
-rw-r--r--manual/PRESENTATION_ExAdv/red_or3x1_test.ys7
5 files changed, 69 insertions, 1 deletions
diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile
index f38bd6ce..673b3a21 100644
--- a/manual/PRESENTATION_ExAdv/Makefile
+++ b/manual/PRESENTATION_ExAdv/Makefile
@@ -1,6 +1,9 @@
-all: select_01.pdf
+all: select_01.pdf red_or3x1.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
+red_or3x1.pdf: red_or3x1_*
+ ../../yosys red_or3x1_test.ys
+
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_cells.v b/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
new file mode 100644
index 00000000..0750a130
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_cells.v
@@ -0,0 +1,5 @@
+module OR3X1(A, B, C, Y);
+ input A, B, C;
+ output Y;
+ assign Y = A | B | C;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_map.v b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
new file mode 100644
index 00000000..24ca9dab
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_map.v
@@ -0,0 +1,48 @@
+module \$reduce_or (A, Y);
+
+ parameter A_SIGNED = 0;
+ parameter A_WIDTH = 0;
+ parameter Y_WIDTH = 0;
+
+ input [A_WIDTH-1:0] A;
+ output [Y_WIDTH-1:0] Y;
+
+ function integer min;
+ input integer a, b;
+ begin
+ if (a < b)
+ min = a;
+ else
+ min = b;
+ end
+ endfunction
+
+ genvar i;
+ generate begin
+ if (A_WIDTH == 0) begin
+ assign Y = 0;
+ end
+ if (A_WIDTH == 1) begin
+ assign Y = A;
+ end
+ if (A_WIDTH == 2) begin
+ wire ybuf;
+ OR3X1 g (.A(A[0]), .B(A[1]), .C(1'b0), .Y(ybuf));
+ assign Y = ybuf;
+ end
+ if (A_WIDTH == 3) begin
+ wire ybuf;
+ OR3X1 g (.A(A[0]), .B(A[1]), .C(A[2]), .Y(ybuf));
+ assign Y = ybuf;
+ end
+ if (A_WIDTH > 3) begin
+ localparam next_stage_sz = (A_WIDTH+2) / 3;
+ wire [next_stage_sz-1:0] next_stage;
+ for (i = 0; i < next_stage_sz; i = i+1) begin
+ localparam bits = min(A_WIDTH - 3*i, 3);
+ assign next_stage[i] = |A[3*i +: bits];
+ end
+ assign Y = |next_stage;
+ end
+ end endgenerate
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_test.v b/manual/PRESENTATION_ExAdv/red_or3x1_test.v
new file mode 100644
index 00000000..bcdd32cb
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_test.v
@@ -0,0 +1,5 @@
+module test (A, Y);
+ input [6:0] A;
+ output Y;
+ assign Y = |A;
+endmodule
diff --git a/manual/PRESENTATION_ExAdv/red_or3x1_test.ys b/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
new file mode 100644
index 00000000..b9234603
--- /dev/null
+++ b/manual/PRESENTATION_ExAdv/red_or3x1_test.ys
@@ -0,0 +1,7 @@
+read_verilog red_or3x1_test.v
+hierarchy -check -top test
+
+techmap -map red_or3x1_map.v;;
+
+splitnets -ports
+show -prefix red_or3x1 -format pdf -notitle -lib red_or3x1_cells.v