1 files changed, 3 insertions, 3 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex
index 0b7d61a4..555ec917 100644
--- a/manual/PRESENTATION_Intro.tex
+++ b/manual/PRESENTATION_Intro.tex
@@ -503,7 +503,7 @@ Commands for executing scripts or entering interactive mode:
 Commands for reading and elaborating the design:
 \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=ys]
     read_ilang           # read modules from ilang file
-    read_verilog         # read modules from verilog file
+    read_verilog         # read modules from Verilog file
     hierarchy            # check, expand and clean up design hierarchy
 \end{lstlisting}
 
@@ -536,7 +536,7 @@ Commands for writing the results:
     write_edif           # write design to EDIF netlist file
     write_ilang          # write design to ilang file
     write_spice          # write design to SPICE netlist file
-    write_verilog        # write design to verilog file
+    write_verilog        # write design to Verilog file
 \end{lstlisting}
 
 \bigskip
@@ -761,7 +761,7 @@ Because of the framework characteristics of Yosys, an increasing number of featu
 become available in one tool. Yosys not only can be used for circuit synthesis but
 also for formal equivalence checking, SAT solving, and for circuit analysis, to
 name just a few other application domains. With proprietary software one needs to
-learn a new tool for each of this applications.
+learn a new tool for each of these applications.
 \end{itemize}
 \end{frame}