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Diffstat (limited to 'manual/PRESENTATION_Intro.tex')
| -rw-r--r-- | manual/PRESENTATION_Intro.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 312cb898..27576647 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -326,7 +326,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des Read Verilog source file and convert to internal representation. }% \only<2>{ - Elaborate the design hierarchy. Should alsways be the first + Elaborate the design hierarchy. Should always be the first command after reading the design. }% \only<3>{ @@ -794,7 +794,7 @@ We need you as a developer: \begin{frame}{\subsecname} \begin{itemize} \item Yosys is a powerful tool and framework for Verilog synthesis. -\item Is uses a command-based interface and can be controlled by scripts. +\item It uses a command-based interface and can be controlled by scripts. \item By combining existing commands and implementing new commands Yosys can be used in a wide range of application far beyond simple synthesis. \end{itemize} |