diff options
Diffstat (limited to 'manual')
-rw-r--r-- | manual/CHAPTER_Eval/grep-it.sh (renamed from manual/FILES_Eval/grep-it.sh) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Eval/openmsp430.prj (renamed from manual/FILES_Eval/openmsp430.prj) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Eval/openmsp430_ys.prj (renamed from manual/FILES_Eval/openmsp430_ys.prj) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Eval/or1200.prj (renamed from manual/FILES_Eval/or1200.prj) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Eval/or1200_ys.prj (renamed from manual/FILES_Eval/or1200_ys.prj) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Eval/run-it.sh (renamed from manual/FILES_Eval/run-it.sh) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Eval/settings.xst (renamed from manual/FILES_Eval/settings.xst) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Prog.tex | 6 | ||||
-rw-r--r-- | manual/CHAPTER_Prog/Makefile (renamed from manual/FILES_Prog/Makefile) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Prog/stubnets.cc (renamed from manual/FILES_Prog/stubnets.cc) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_Prog/test.v (renamed from manual/FILES_Prog/test.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt.tex | 12 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/always01.v (renamed from manual/FILES_StateOfTheArt/always01.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/always01_pub.v (renamed from manual/FILES_StateOfTheArt/always01_pub.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/always02.v (renamed from manual/FILES_StateOfTheArt/always02.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/always02_pub.v (renamed from manual/FILES_StateOfTheArt/always02_pub.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/always03.v (renamed from manual/FILES_StateOfTheArt/always03.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/arrays01.v (renamed from manual/FILES_StateOfTheArt/arrays01.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/cmp_tbdata.c (renamed from manual/FILES_StateOfTheArt/cmp_tbdata.c) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/forgen01.v (renamed from manual/FILES_StateOfTheArt/forgen01.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/forgen02.v (renamed from manual/FILES_StateOfTheArt/forgen02.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch (renamed from manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch (renamed from manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/simlib_hana.v (renamed from manual/FILES_StateOfTheArt/simlib_hana.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/simlib_icarus.v (renamed from manual/FILES_StateOfTheArt/simlib_icarus.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/simlib_yosys.v (renamed from manual/FILES_StateOfTheArt/simlib_yosys.v) | 0 | ||||
-rw-r--r-- | manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch (renamed from manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch) | 0 | ||||
-rwxr-xr-x | manual/CHAPTER_StateOfTheArt/synth.sh (renamed from manual/FILES_StateOfTheArt/synth.sh) | 0 | ||||
-rwxr-xr-x | manual/CHAPTER_StateOfTheArt/validate_tb.sh (renamed from manual/FILES_StateOfTheArt/validate_tb.sh) | 0 |
29 files changed, 9 insertions, 9 deletions
diff --git a/manual/FILES_Eval/grep-it.sh b/manual/CHAPTER_Eval/grep-it.sh index f92eb52c..f92eb52c 100644 --- a/manual/FILES_Eval/grep-it.sh +++ b/manual/CHAPTER_Eval/grep-it.sh diff --git a/manual/FILES_Eval/openmsp430.prj b/manual/CHAPTER_Eval/openmsp430.prj index cb8cd271..cb8cd271 100644 --- a/manual/FILES_Eval/openmsp430.prj +++ b/manual/CHAPTER_Eval/openmsp430.prj diff --git a/manual/FILES_Eval/openmsp430_ys.prj b/manual/CHAPTER_Eval/openmsp430_ys.prj index 0009c99d..0009c99d 100644 --- a/manual/FILES_Eval/openmsp430_ys.prj +++ b/manual/CHAPTER_Eval/openmsp430_ys.prj diff --git a/manual/FILES_Eval/or1200.prj b/manual/CHAPTER_Eval/or1200.prj index 9496874e..9496874e 100644 --- a/manual/FILES_Eval/or1200.prj +++ b/manual/CHAPTER_Eval/or1200.prj diff --git a/manual/FILES_Eval/or1200_ys.prj b/manual/CHAPTER_Eval/or1200_ys.prj index 4dd5f41a..4dd5f41a 100644 --- a/manual/FILES_Eval/or1200_ys.prj +++ b/manual/CHAPTER_Eval/or1200_ys.prj diff --git a/manual/FILES_Eval/run-it.sh b/manual/CHAPTER_Eval/run-it.sh index b4a67ceb..b4a67ceb 100644 --- a/manual/FILES_Eval/run-it.sh +++ b/manual/CHAPTER_Eval/run-it.sh diff --git a/manual/FILES_Eval/settings.xst b/manual/CHAPTER_Eval/settings.xst index 2f381d09..2f381d09 100644 --- a/manual/FILES_Eval/settings.xst +++ b/manual/CHAPTER_Eval/settings.xst diff --git a/manual/CHAPTER_Prog.tex b/manual/CHAPTER_Prog.tex index b6157aa1..3918594a 100644 --- a/manual/CHAPTER_Prog.tex +++ b/manual/CHAPTER_Prog.tex @@ -13,9 +13,9 @@ with an example module. \section{Example Module} -\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{FILES_Prog/stubnets.cc} +\lstinputlisting[title=stubnets.cc,numbers=left,frame=single,language=C++]{CHAPTER_Prog/stubnets.cc} -\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{FILES_Prog/Makefile} +\lstinputlisting[title=Makefile,numbers=left,frame=single,language=make]{CHAPTER_Prog/Makefile} -\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{FILES_Prog/test.v} +\lstinputlisting[title=test.v,numbers=left,frame=single,language=Verilog]{CHAPTER_Prog/test.v} diff --git a/manual/FILES_Prog/Makefile b/manual/CHAPTER_Prog/Makefile index 8e326bdc..8e326bdc 100644 --- a/manual/FILES_Prog/Makefile +++ b/manual/CHAPTER_Prog/Makefile diff --git a/manual/FILES_Prog/stubnets.cc b/manual/CHAPTER_Prog/stubnets.cc index 1c71f78b..1c71f78b 100644 --- a/manual/FILES_Prog/stubnets.cc +++ b/manual/CHAPTER_Prog/stubnets.cc diff --git a/manual/FILES_Prog/test.v b/manual/CHAPTER_Prog/test.v index 201f7500..201f7500 100644 --- a/manual/FILES_Prog/test.v +++ b/manual/CHAPTER_Prog/test.v diff --git a/manual/CHAPTER_StateOfTheArt.tex b/manual/CHAPTER_StateOfTheArt.tex index d6a5c9b1..7e62230e 100644 --- a/manual/CHAPTER_StateOfTheArt.tex +++ b/manual/CHAPTER_StateOfTheArt.tex @@ -55,18 +55,18 @@ with a summary of the results. \begin{figure}[t!] \begin{minipage}{7.7cm} - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always01_pub.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always01_pub.v} \end{minipage} \hfill \begin{minipage}{7.7cm} - \lstinputlisting[frame=single,language=Verilog]{FILES_StateOfTheArt/always02_pub.v} + \lstinputlisting[frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always02_pub.v} \end{minipage} \caption{1st and 2nd Verilog always examples} \label{fig:StateOfTheArt_always12} \end{figure} \begin{figure}[!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/always03.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/always03.v} \caption{3rd Verilog always example} \label{fig:StateOfTheArt_always3} \end{figure} @@ -107,7 +107,7 @@ The first example is only using the most fundamental Verilog features. All tools under test were able to successfully synthesize this design. \begin{figure}[b!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/arrays01.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/arrays01.v} \caption{Verilog array example} \label{fig:StateOfTheArt_arrays} \end{figure} @@ -155,7 +155,7 @@ For this design HANA, vl2m and ODIN-II generate error messages indicating that arrays are not supported. \begin{figure}[t!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen01.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen01.v} \caption{Verilog for loop example} \label{fig:StateOfTheArt_for} \end{figure} @@ -171,7 +171,7 @@ by continuing tests on this aspect of Verilog synthesis such as synthesis of dua memories, correct handling of write collisions, and so forth. \begin{figure}[t!] - \lstinputlisting[numbers=left,frame=single,language=Verilog]{FILES_StateOfTheArt/forgen02.v} + \lstinputlisting[numbers=left,frame=single,language=Verilog]{CHAPTER_StateOfTheArt/forgen02.v} \caption{Verilog generate example} \label{fig:StateOfTheArt_gen} \end{figure} diff --git a/manual/FILES_StateOfTheArt/always01.v b/manual/CHAPTER_StateOfTheArt/always01.v index 4719ed47..4719ed47 100644 --- a/manual/FILES_StateOfTheArt/always01.v +++ b/manual/CHAPTER_StateOfTheArt/always01.v diff --git a/manual/FILES_StateOfTheArt/always01_pub.v b/manual/CHAPTER_StateOfTheArt/always01_pub.v index 6a6a4b23..6a6a4b23 100644 --- a/manual/FILES_StateOfTheArt/always01_pub.v +++ b/manual/CHAPTER_StateOfTheArt/always01_pub.v diff --git a/manual/FILES_StateOfTheArt/always02.v b/manual/CHAPTER_StateOfTheArt/always02.v index 63f1ce31..63f1ce31 100644 --- a/manual/FILES_StateOfTheArt/always02.v +++ b/manual/CHAPTER_StateOfTheArt/always02.v diff --git a/manual/FILES_StateOfTheArt/always02_pub.v b/manual/CHAPTER_StateOfTheArt/always02_pub.v index 91f1ca16..91f1ca16 100644 --- a/manual/FILES_StateOfTheArt/always02_pub.v +++ b/manual/CHAPTER_StateOfTheArt/always02_pub.v diff --git a/manual/FILES_StateOfTheArt/always03.v b/manual/CHAPTER_StateOfTheArt/always03.v index 53386acd..53386acd 100644 --- a/manual/FILES_StateOfTheArt/always03.v +++ b/manual/CHAPTER_StateOfTheArt/always03.v diff --git a/manual/FILES_StateOfTheArt/arrays01.v b/manual/CHAPTER_StateOfTheArt/arrays01.v index bd0eda29..bd0eda29 100644 --- a/manual/FILES_StateOfTheArt/arrays01.v +++ b/manual/CHAPTER_StateOfTheArt/arrays01.v diff --git a/manual/FILES_StateOfTheArt/cmp_tbdata.c b/manual/CHAPTER_StateOfTheArt/cmp_tbdata.c index b188144d..b188144d 100644 --- a/manual/FILES_StateOfTheArt/cmp_tbdata.c +++ b/manual/CHAPTER_StateOfTheArt/cmp_tbdata.c diff --git a/manual/FILES_StateOfTheArt/forgen01.v b/manual/CHAPTER_StateOfTheArt/forgen01.v index 70ee7e66..70ee7e66 100644 --- a/manual/FILES_StateOfTheArt/forgen01.v +++ b/manual/CHAPTER_StateOfTheArt/forgen01.v diff --git a/manual/FILES_StateOfTheArt/forgen02.v b/manual/CHAPTER_StateOfTheArt/forgen02.v index 14af070c..14af070c 100644 --- a/manual/FILES_StateOfTheArt/forgen02.v +++ b/manual/CHAPTER_StateOfTheArt/forgen02.v diff --git a/manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch index 63a03e59..63a03e59 100644 --- a/manual/FILES_StateOfTheArt/iverilog-0.8.7-buildfixes.patch +++ b/manual/CHAPTER_StateOfTheArt/iverilog-0.8.7-buildfixes.patch diff --git a/manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch index 4b44320f..4b44320f 100644 --- a/manual/FILES_StateOfTheArt/mvsis-1.3.6-buildfixes.patch +++ b/manual/CHAPTER_StateOfTheArt/mvsis-1.3.6-buildfixes.patch diff --git a/manual/FILES_StateOfTheArt/simlib_hana.v b/manual/CHAPTER_StateOfTheArt/simlib_hana.v index fc82f138..fc82f138 100644 --- a/manual/FILES_StateOfTheArt/simlib_hana.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_hana.v diff --git a/manual/FILES_StateOfTheArt/simlib_icarus.v b/manual/CHAPTER_StateOfTheArt/simlib_icarus.v index fdd7ef61..fdd7ef61 100644 --- a/manual/FILES_StateOfTheArt/simlib_icarus.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_icarus.v diff --git a/manual/FILES_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v index a2df8f64..a2df8f64 100644 --- a/manual/FILES_StateOfTheArt/simlib_yosys.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v diff --git a/manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch b/manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch index ad957d6b..ad957d6b 100644 --- a/manual/FILES_StateOfTheArt/sis-1.3.6-buildfixes.patch +++ b/manual/CHAPTER_StateOfTheArt/sis-1.3.6-buildfixes.patch diff --git a/manual/FILES_StateOfTheArt/synth.sh b/manual/CHAPTER_StateOfTheArt/synth.sh index 3a7524a2..3a7524a2 100755 --- a/manual/FILES_StateOfTheArt/synth.sh +++ b/manual/CHAPTER_StateOfTheArt/synth.sh diff --git a/manual/FILES_StateOfTheArt/validate_tb.sh b/manual/CHAPTER_StateOfTheArt/validate_tb.sh index b6409eb1..b6409eb1 100755 --- a/manual/FILES_StateOfTheArt/validate_tb.sh +++ b/manual/CHAPTER_StateOfTheArt/validate_tb.sh |