diff options
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/PRESENTATION_Intro.tex | 32 | ||||
| -rw-r--r-- | manual/PRESENTATION_Intro/counter.ys | 8 |
2 files changed, 36 insertions, 4 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 6693ad2f..6f3ea755 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -374,3 +374,35 @@ clean \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_Intro/counter_03.pdf} \end{frame} +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{More Yosys Commands} + +\begin{frame}{\subsecname{} -- TBD} +TBD +\end{frame} + +\subsection{More Verilog Examples} + +\begin{frame}{\subsecname{} -- TBD} +TBD +\end{frame} + +\subsection{Verification} + +\begin{frame}{\subsecname{} -- VlogHammer} +TBD +\end{frame} + +\begin{frame}{\subsecname{} -- yosys-bigsim} +TBD +\end{frame} + +\subsection{Benefits of Open Source HDL Synthesis} + +\begin{frame}{\subsecname} +TBD +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + diff --git a/manual/PRESENTATION_Intro/counter.ys b/manual/PRESENTATION_Intro/counter.ys index 68fe0308..bcfe387e 100644 --- a/manual/PRESENTATION_Intro/counter.ys +++ b/manual/PRESENTATION_Intro/counter.ys @@ -2,17 +2,17 @@ read_verilog counter.v hierarchy -check -top counter -show -format pdf -prefix counter_00 +show -stretch -format pdf -prefix counter_00 # the high-level stuff proc; opt; memory; opt; fsm; opt -show -format pdf -prefix counter_01 +show -stretch -format pdf -prefix counter_01 # mapping to internal cell library techmap; splitnets -ports; opt -show -format pdf -prefix counter_02 +show -stretch -format pdf -prefix counter_02 # mapping flip-flops to mycells.lib dfflibmap -liberty mycells.lib @@ -23,4 +23,4 @@ abc -liberty mycells.lib # cleanup clean -show -lib mycells.v -format pdf -prefix counter_03 +show -stretch -lib mycells.v -format pdf -prefix counter_03 |