diff options
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/PRESENTATION_Intro.tex | 78 | ||||
| -rw-r--r-- | manual/presentation.tex | 19 |
2 files changed, 97 insertions, 0 deletions
diff --git a/manual/PRESENTATION_Intro.tex b/manual/PRESENTATION_Intro.tex index 40b3c226..7697266d 100644 --- a/manual/PRESENTATION_Intro.tex +++ b/manual/PRESENTATION_Intro.tex @@ -599,6 +599,23 @@ endmodule %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Currently unsupported Verilog-2005 language features} + +\begin{frame}{\subsecname} +\begin{itemize} +\item Multi-dimensional arrays (memories) +\item Writing to arrays using bit- and part-selects (todo for 0.4.0) +\item The wor/wand wire types (maybe for 0.4.0) +\item Tri-state logic + +\bigskip +\item Latched logic (is synthesized as logic with feedback loops) +\item Some non-synthesizable features that should be ignored in synthesis are not supported by the parser and cause a parser error (file a bug report if you encounter this problem) +\end{itemize} +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \subsection{Verification of Yosys} \begin{frame}{\subsecname} @@ -744,6 +761,67 @@ but also formal verification, reverse engineering, ...} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Projects (that I know of) using Yosys} + +\begin{frame}{\subsecname{} -- (1/2)} +\begin{itemize} +\item Ongoing PhD project on coarse grain synthesis \\ +{\setlength{\parindent}{0.5cm}\footnotesize +Johann Glaser and Clifford Wolf. Methodology and Example-Driven Interconnect +Synthesis for Designing Heterogeneous Coarse-Grain Reconfigurable +Architectures. In Jan Haase, editor, \it Models, Methods, and Tools for Complex +Chip Design. Lecture Notes in Electrical Engineering. Volume 265, 2014, pp +201-221. Springer, 2013.} + +\bigskip +\item I know several people that use Yosys simply as Verilog frontend for other +flows (using either the BLIF and BTOR backends). + +\bigskip +\item I know some analog chip designers that use Yosys for small digital +control logic because it is simpler than setting up a commercial flow. +\end{itemize} +\end{frame} + +\begin{frame}{\subsecname{} -- (2/2)} +\begin{itemize} +\item Efabless +\begin{itemize} +\smallskip \item Not much information on the website (\url{http://efabless.com}) yet. +\smallskip \item Very cheap 180nm prototyping process (partnering with various fabs) +\smallskip \item A semiconductor company, NOT an EDA company +\smallskip \item Web-based design environment +\smallskip \item HDL Synthesis using Yosys +\smallskip \item Custom place\&route tool + +\bigskip +\item efabless is building an Open Source IC as reference design. \\ +\hskip1cm (to be announced soon: \url{http://www.openic.io}) +\end{itemize} +\end{itemize} +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Supported Platforms} + +\begin{frame}{\subsecname} +\begin{itemize} +\item Main development OS: Kubuntu 14.04 +\item There is a PPA for ubuntu (not maintained by me) +\item Any current Debian-based system should work out of the box +\item When building on other Linux distributions: +\begin{itemize} +\item Needs compiler with some C++11 support +\item Post to the subreddit if you get stuck +\end{itemize} +\item Ported to OS X (Darwin) and OpenBSD +\item No win32 support (yet) +\end{itemize} +\end{frame} + +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + \subsection{Other Open Source Tools} \begin{frame}{\subsecname} diff --git a/manual/presentation.tex b/manual/presentation.tex index d098e815..a76a1c00 100644 --- a/manual/presentation.tex +++ b/manual/presentation.tex @@ -122,6 +122,25 @@ non-synthesis applications (such as formal equivialence checking) and writing extensions to Yosys using the C++ API. \end{frame} +\section{About me} +\begin{frame}{About me} +Hi! I'm Clifford Wolf. + +\bigskip +I like writing open source software. For example: +\begin{itemize} +\item Yosys +\item OpenSCAD (now maintained by Marius Kintel) +\item SPL (a not very popular scripting language) +\item EmbedVM (a very simple colipler+vm for 8 bit micros) +\item Lib(X)SVF (a library to play SVF/XSVF files over JTAG, used at LHC) +\item ROCK Linux (inactive since 2010) +\end{itemize} + +\bigskip +What do I do for a living? Ask me off the record.. +\end{frame} + \section{Outline} \begin{frame}{Outline} Yosys is an Open Source Verilog synthesis tool, and more. |