diff options
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/PRESENTATION_ExSyn.tex | 32 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/.gitignore | 1 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/Makefile | 12 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_00.v | 7 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_00.ys | 3 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_01.v | 8 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_01.ys | 3 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_02.v | 10 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn/proc_02.ys | 3 | ||||
| -rwxr-xr-x | manual/presentation.sh | 1 |
10 files changed, 80 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index 3440bbf1..66ee1804 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -101,7 +101,39 @@ proc_clean # if all went fine, this should remove all the processes Many commands can not operate on modules with ``processes'' in them. Usually a call to {\tt proc} is the first command in the actual synthesis procedure after design elaboration. +\end{frame} + +\begin{frame}[fragile]{\subsecname{} -- Example 1/TBD} +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_00.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_00.ys} +\end{columns} +% \includegraphics[width=\linewidth,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf} +\hfil\includegraphics[width=8cm,trim=0 0cm 0 0cm]{PRESENTATION_ExSyn/proc_00.pdf} +\end{frame} + +\begin{frame}[t, fragile]{\subsecname{} -- Example 2/TBD} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -2.5cm]{PRESENTATION_ExSyn/proc_01.pdf}} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_01.v} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_01.ys} +\end{columns} +\end{frame} +\begin{frame}[t, fragile]{\subsecname{} -- Example 3/TBD} +\vbox to 0cm{\includegraphics[width=\linewidth,trim=0cm 0cm 0cm -1.5cm]{PRESENTATION_ExSyn/proc_02.pdf}} +\vskip-1cm +\begin{columns} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single]{PRESENTATION_ExSyn/proc_02.ys} +\column[t]{5cm} +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExSyn/proc_02.v} +\end{columns} \end{frame} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% diff --git a/manual/PRESENTATION_ExSyn/.gitignore b/manual/PRESENTATION_ExSyn/.gitignore new file mode 100644 index 00000000..cf658897 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/.gitignore @@ -0,0 +1 @@ +*.dot diff --git a/manual/PRESENTATION_ExSyn/Makefile b/manual/PRESENTATION_ExSyn/Makefile new file mode 100644 index 00000000..0450075d --- /dev/null +++ b/manual/PRESENTATION_ExSyn/Makefile @@ -0,0 +1,12 @@ + +all: proc_00.pdf proc_01.pdf proc_02.pdf + +proc_00.pdf: proc_00.v proc_00.ys + ../../yosys -p 'script proc_00.ys; show -notitle -prefix proc_00 -format pdf' + +proc_01.pdf: proc_01.v proc_01.ys + ../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format pdf' + +proc_02.pdf: proc_02.v proc_02.ys + ../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format pdf' + diff --git a/manual/PRESENTATION_ExSyn/proc_00.v b/manual/PRESENTATION_ExSyn/proc_00.v new file mode 100644 index 00000000..61286319 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_00.v @@ -0,0 +1,7 @@ +module test(input D, C, R, output reg Q); + always @(posedge C, posedge R) + if (R) + Q <= 0; + else + Q <= D; +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_00.ys b/manual/PRESENTATION_ExSyn/proc_00.ys new file mode 100644 index 00000000..6440efd3 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_00.ys @@ -0,0 +1,3 @@ +read_verilog proc_00.v +hierarchy -check -top test +proc;; diff --git a/manual/PRESENTATION_ExSyn/proc_01.v b/manual/PRESENTATION_ExSyn/proc_01.v new file mode 100644 index 00000000..8e440f6c --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_01.v @@ -0,0 +1,8 @@ +module test(input D, C, R, RV, + output reg Q); + always @(posedge C, posedge R) + if (R) + Q <= RV; + else + Q <= D; +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_01.ys b/manual/PRESENTATION_ExSyn/proc_01.ys new file mode 100644 index 00000000..c22a2fd5 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_01.ys @@ -0,0 +1,3 @@ +read_verilog proc_01.v +hierarchy -check -top test +proc;; diff --git a/manual/PRESENTATION_ExSyn/proc_02.v b/manual/PRESENTATION_ExSyn/proc_02.v new file mode 100644 index 00000000..a89c965e --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_02.v @@ -0,0 +1,10 @@ +module test(input A, B, C, D, E, + output reg Y); + always @* begin + Y <= A; + if (B) + Y <= C; + if (D) + Y <= E; + end +endmodule diff --git a/manual/PRESENTATION_ExSyn/proc_02.ys b/manual/PRESENTATION_ExSyn/proc_02.ys new file mode 100644 index 00000000..823b18d6 --- /dev/null +++ b/manual/PRESENTATION_ExSyn/proc_02.ys @@ -0,0 +1,3 @@ +read_verilog proc_02.v +hierarchy -check -top test +proc;; diff --git a/manual/presentation.sh b/manual/presentation.sh index 530d0b8c..6719f916 100755 --- a/manual/presentation.sh +++ b/manual/presentation.sh @@ -27,6 +27,7 @@ PDFTEX_OPT="-shell-escape -halt-on-error" if ! $fast_mode; then md5sum *.aux *.snm *.nav *.toc > autoloop.old make -C PRESENTATION_Intro + make -C PRESENTATION_ExSyn fi set -ex |