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-rw-r--r--passes/abc/abc.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 8f873867..5aa13572 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -447,7 +447,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
extract_cell(c);
for (auto &wire_it : module->wires) {
- if (wire_it.second->port_id > 0)
+ if (wire_it.second->port_id > 0 || wire_it.second->get_bool_attribute("\\keep"))
mark_port(RTLIL::SigSpec(wire_it.second));
}