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-rw-r--r--passes/abc/abc.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index fd56668c..b18f8835 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -166,7 +166,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff)
return;
}
- if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR", "$_XOR_", "$_XNOR_"))
+ if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
{
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_b = cell->getPort("\\B");