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-rw-r--r--passes/abc/abc.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index c53c4450..4d9a6c13 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
assert(c.width == 1);
newsig.append(module->wires[remap_name(c.wire->name)]);
}
- cell->connections()[conn.first] = newsig;
+ cell->set(conn.first, newsig);
}
design->select(module, cell);
}