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-rw-r--r--passes/abc/abc.cc2
-rw-r--r--passes/abc/blifparse.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index c53c4450..4d9a6c13 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
assert(c.width == 1);
newsig.append(module->wires[remap_name(c.wire->name)]);
}
- cell->connections()[conn.first] = newsig;
+ cell->set(conn.first, newsig);
}
design->select(module, cell);
}
diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index e5bfb98b..45a9ac76 100644
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
*(q++) = 0;
if (module->wires.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q));
- cell->connections()[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
+ cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q)));
}
continue;
}