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-rw-r--r--passes/cmds/add.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc
index ce8ecc32..1401193f 100644
--- a/passes/cmds/add.cc
+++ b/passes/cmds/add.cc
@@ -75,10 +75,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
continue;
if (mod->get_bool_attribute("\\blackbox"))
continue;
- if (it.second->connections_.count(name) > 0)
+ if (it.second->connections().count(name) > 0)
continue;
- it.second->connections_[name] = wire;
+ it.second->set(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
}
}