diff options
Diffstat (limited to 'passes/cmds')
| -rw-r--r-- | passes/cmds/connwrappers.cc | 6 | ||||
| -rw-r--r-- | passes/cmds/show.cc | 24 | ||||
| -rw-r--r-- | passes/cmds/splice.cc | 8 | ||||
| -rw-r--r-- | passes/cmds/splitnets.cc | 2 |
4 files changed, 21 insertions, 19 deletions
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 5125ff5e..aac11716 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -30,8 +30,8 @@ struct ConnwrappersWorker bool is_signed; }; - std::set<std::string> decl_celltypes; - std::map<std::pair<std::string, std::string>, portdecl_t> decls; + std::set<RTLIL::IdString> decl_celltypes; + std::map<std::pair<RTLIL::IdString, RTLIL::IdString>, portdecl_t> decls; void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam) { @@ -76,7 +76,7 @@ struct ConnwrappersWorker for (auto &conn : cell->connections()) { - std::pair<std::string, std::string> key(cell->type, conn.first); + std::pair<RTLIL::IdString, RTLIL::IdString> key(cell->type, conn.first); if (!decls.count(key)) continue; diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index a2dd8051..bbc0ff44 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -111,7 +111,7 @@ struct ShowWorker return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits); } - const char *findColor(std::string member_name) + const char *findColor(RTLIL::IdString member_name) { for (auto &s : color_selections) if (s.second.selected_member(module->name, member_name)) { @@ -121,20 +121,22 @@ struct ShowWorker return ""; } - const char *findLabel(std::string member_name) + const char *findLabel(RTLIL::IdString member_name) { for (auto &s : label_selections) - if (s.second.selected_member(module->name, RTLIL::escape_id(member_name))) + if (s.second.selected_member(module->name, member_name)) return escape(s.first); return escape(member_name, true); } - const char *escape(std::string id, bool is_name = false) + const char *escape(RTLIL::IdString id, bool is_name = false) { - if (id.size() == 0) + std::string id_str = id.str(); + + if (id_str.size() == 0) return ""; - if (id[0] == '$' && is_name) { + if (id_str[0] == '$' && is_name) { if (enumerateIds) { if (autonames.count(id) == 0) { autonames[id] = autonames.size() + 1; @@ -142,17 +144,17 @@ struct ShowWorker } id = stringf("_%d_", autonames[id]); } else if (abbreviateIds) { - const char *p = id.c_str(); + const char *p = id_str.c_str(); const char *q = strrchr(p, '$'); - id = std::string(q); + id_str = std::string(q); } } - if (id[0] == '\\') - id = id.substr(1); + if (id_str[0] == '\\') + id_str = id_str.substr(1); std::string str; - for (char ch : id) { + for (char ch : id_str) { if (ch == '\\' || ch == '"') str += "\\"; str += ch; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 07c6150c..ca71f7d8 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -33,8 +33,8 @@ struct SpliceWorker bool sel_by_wire; bool sel_any_bit; bool no_outputs; - std::set<std::string> ports; - std::set<std::string> no_ports; + std::set<RTLIL::IdString> ports; + std::set<RTLIL::IdString> no_ports; CellTypes ct; SigMap sigmap; @@ -224,7 +224,7 @@ struct SpliceWorker for (auto &it : rework_wires) { - std::string orig_name = it.first->name; + RTLIL::IdString orig_name = it.first->name; module->rename(it.first, NEW_ID); RTLIL::Wire *new_port = module->addWire(orig_name, it.first); @@ -283,7 +283,7 @@ struct SplicePass : public Pass { bool sel_by_wire = false; bool sel_any_bit = false; bool no_outputs = false; - std::set<std::string> ports, no_ports; + std::set<RTLIL::IdString> ports, no_ports; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 6b1dbe13..a3daf239 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -28,7 +28,7 @@ struct SplitnetsWorker void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format) { - std::string new_wire_name = wire->name; + std::string new_wire_name = wire->name.str(); if (format.size() > 0) new_wire_name += format.substr(0, 1); |