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-rw-r--r--passes/cmds/rename.cc14
-rw-r--r--passes/cmds/splice.cc10
2 files changed, 9 insertions, 15 deletions
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 519dce45..721d5c98 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -31,21 +31,15 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
for (auto &it : module->wires)
if (it.first == from_name) {
- RTLIL::Wire *wire = it.second;
- log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str());
- module->wires.erase(wire->name);
- wire->name = to_name;
- module->add(wire);
+ log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
+ module->rename(it.second, to_name);
return;
}
for (auto &it : module->cells)
if (it.first == from_name) {
- RTLIL::Cell *cell = it.second;
- log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str());
- module->cells.erase(cell->name);
- cell->name = to_name;
- module->add(cell);
+ log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
+ module->rename(it.second, to_name);
return;
}
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 8b7e0406..61de4406 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -224,14 +224,14 @@ struct SpliceWorker
for (auto &it : rework_wires)
{
- module->wires.erase(it.first->name);
- RTLIL::Wire *new_port = new RTLIL::Wire(*it.first);
- it.first->name = NEW_ID;
+ std::string orig_name = it.first->name;
+ module->rename(it.first, NEW_ID);
+
+ RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
it.first->port_id = 0;
it.first->port_input = false;
it.first->port_output = false;
- module->add(it.first);
- module->add(new_port);
+
module->connect(RTLIL::SigSig(new_port, it.second));
}
}