diff options
Diffstat (limited to 'passes/equiv')
| -rw-r--r-- | passes/equiv/equiv_miter.cc | 2 | ||||
| -rw-r--r-- | passes/equiv/equiv_purge.cc | 5 |
2 files changed, 4 insertions, 3 deletions
diff --git a/passes/equiv/equiv_miter.cc b/passes/equiv/equiv_miter.cc index 34318dec..982176c4 100644 --- a/passes/equiv/equiv_miter.cc +++ b/passes/equiv/equiv_miter.cc @@ -156,7 +156,7 @@ struct EquivMiterWorker struct RewriteSigSpecWorker { RTLIL::Module * mod; void operator()(SigSpec &sig) { - vector<RTLIL::SigChunk> chunks = sig.chunks(); + vector<SigChunk> chunks = sig.chunks(); for (auto &c : chunks) if (c.wire != NULL) c.wire = mod->wires_.at(c.wire->name); diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc index e14ffe31..f4141ad4 100644 --- a/passes/equiv/equiv_purge.cc +++ b/passes/equiv/equiv_purge.cc @@ -162,8 +162,9 @@ struct EquivPurgeWorker srcsig.sort_and_unify(); - for (SigSpec sig : srcsig.chunks()) - rewrite_sigmap.add(sig, make_input(sig)); + for (SigChunk chunk : srcsig.chunks()) + if (chunk.wire != nullptr) + rewrite_sigmap.add(chunk, make_input(chunk)); for (auto cell : module->cells()) if (cell->type == "$equiv") |