1 files changed, 17 insertions, 17 deletions

diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 718f779b..cf2075fb 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -58,9 +58,9 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
 			log("  unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
 			return false;
 		}
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_s = assign_map(cell->get("\\S"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_s = assign_map(cell->getPort("\\S"));
 		if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
 			do {
 				if (sig_a.is_fully_def())
@@ -183,12 +183,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 		if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
 			continue;
 		log("  found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
-		RTLIL::SigSpec sig_q = assign_map(cell->get("\\Q"));
-		RTLIL::SigSpec sig_d = assign_map(cell->get("\\D"));
-		clk = cell->get("\\CLK");
+		RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q"));
+		RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D"));
+		clk = cell->getPort("\\CLK");
 		clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
 		if (cell->type == "$adff") {
-			arst = cell->get("\\ARST");
+			arst = cell->getPort("\\ARST");
 			arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
 			reset_state = cell->parameters["\\ARST_VALUE"];
 		}
@@ -224,9 +224,9 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2trigger.find(dff_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		RTLIL::SigSpec sig_a = assign_map(cell->get("\\A"));
-		RTLIL::SigSpec sig_b = assign_map(cell->get("\\B"));
-		RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y"));
+		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+		RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y"));
 		if (cellport.second == "\\A" && !sig_b.is_fully_const())
 			continue;
 		if (cellport.second == "\\B" && !sig_a.is_fully_const())
@@ -271,12 +271,12 @@ static void extract_fsm(RTLIL::Wire *wire)
 	// create fsm cell
 
 	RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
-	fsm_cell->set("\\CLK", clk);
-	fsm_cell->set("\\ARST", arst);
+	fsm_cell->setPort("\\CLK", clk);
+	fsm_cell->setPort("\\ARST", arst);
 	fsm_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity ? 1 : 0, 1);
 	fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
-	fsm_cell->set("\\CTRL_IN", ctrl_in);
-	fsm_cell->set("\\CTRL_OUT", ctrl_out);
+	fsm_cell->setPort("\\CTRL_IN", ctrl_in);
+	fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
 	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
 	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
@@ -294,7 +294,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	sig2driver.find(ctrl_out, cellport_list);
 	for (auto &cellport : cellport_list) {
 		RTLIL::Cell *cell = module->cells_.at(cellport.first);
-		RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second));
+		RTLIL::SigSpec port_sig = assign_map(cell->getPort(cellport.second));
 		RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out);
 		RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), autoidx++), unconn_sig.size());
 		port_sig.replace(unconn_sig, RTLIL::SigSpec(unconn_wire), &cell->connections_[cellport.second]);
@@ -347,8 +347,8 @@ struct FsmExtractPass : public Pass {
 						assign_map.apply(sig);
 						sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));
 					}
-					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") &&
-							cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
+					if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->hasPort("\\Y") &&
+							cell_it.second->getPort("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) {
 						RTLIL::SigSpec sig = conn_it.second;
 						assign_map.apply(sig);
 						sig2trigger.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first));