diff options
Diffstat (limited to 'passes/fsm')
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_export.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_info.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_map.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_opt.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_recode.cc | 2 |
8 files changed, 8 insertions, 8 deletions
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index e1528f31..a619cf57 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -148,7 +148,7 @@ struct FsmDetectPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 40ec55c1..f107366d 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass { log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 129e7f9a..f84f372a 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -174,7 +174,7 @@ struct FsmExportPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 64b01064..99352b10 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 4526939c..45d68a90 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass { log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f6ef12a7..8b9ad6be 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -309,7 +309,7 @@ struct FsmMapPass : public Pass { log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 165b0974..9d9156ae 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -288,7 +288,7 @@ struct FsmOptPass : public Pass { log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second)) diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 1b2eeb23..40fed130 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -144,7 +144,7 @@ struct FsmRecodePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) |