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-rw-r--r--passes/memory/Makefile.inc6
-rw-r--r--passes/memory/memory.cc40
-rw-r--r--passes/memory/memory_collect.cc182
-rw-r--r--passes/memory/memory_dff.cc200
-rw-r--r--passes/memory/memory_map.cc334
5 files changed, 762 insertions, 0 deletions
diff --git a/passes/memory/Makefile.inc b/passes/memory/Makefile.inc
new file mode 100644
index 00000000..cffdefe8
--- /dev/null
+++ b/passes/memory/Makefile.inc
@@ -0,0 +1,6 @@
+
+OBJS += passes/memory/memory.o
+OBJS += passes/memory/memory_dff.o
+OBJS += passes/memory/memory_collect.o
+OBJS += passes/memory/memory_map.o
+
diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
new file mode 100644
index 00000000..c5533b63
--- /dev/null
+++ b/passes/memory/memory.cc
@@ -0,0 +1,40 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <stdlib.h>
+#include <stdio.h>
+
+struct MemoryPass : public Pass {
+ MemoryPass() : Pass("memory") { }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ {
+ log_header("Executing MEMORY pass.\n");
+ log_push();
+
+ extra_args(args, 1, design);
+ Pass::call(design, "memory_dff");
+ Pass::call(design, "memory_collect");
+ Pass::call(design, "memory_map");
+
+ log_pop();
+ }
+} MemoryPass;
+
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
new file mode 100644
index 00000000..b89b9769
--- /dev/null
+++ b/passes/memory/memory_collect.cc
@@ -0,0 +1,182 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <sstream>
+#include <stdlib.h>
+#include <assert.h>
+
+static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
+{
+ log("Collecting $memrd and $memwr for memory `%s' in module `%s':\n",
+ memory->name.c_str(), module->name.c_str());
+
+ int addr_bits = 0;
+ while ((1 << addr_bits) < memory->size)
+ addr_bits++;
+
+ int wr_ports = 0;
+ RTLIL::SigSpec sig_wr_clk;
+ RTLIL::SigSpec sig_wr_clk_enable;
+ RTLIL::SigSpec sig_wr_clk_polarity;
+ RTLIL::SigSpec sig_wr_addr;
+ RTLIL::SigSpec sig_wr_data;
+ RTLIL::SigSpec sig_wr_en;
+
+ int rd_ports = 0;
+ RTLIL::SigSpec sig_rd_clk;
+ RTLIL::SigSpec sig_rd_clk_enable;
+ RTLIL::SigSpec sig_rd_clk_polarity;
+ RTLIL::SigSpec sig_rd_addr;
+ RTLIL::SigSpec sig_rd_data;
+
+ std::vector<std::string> del_cell_ids;
+
+ for (auto &cell_it : module->cells)
+ {
+ RTLIL::Cell *cell = cell_it.second;
+
+ if (cell->type == "$memwr" && cell->parameters["\\MEMID"].str == memory->name)
+ {
+ wr_ports++;
+ del_cell_ids.push_back(cell->name);
+
+ RTLIL::SigSpec clk = cell->connections["\\CLK"];
+ RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
+ RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
+ RTLIL::SigSpec addr = cell->connections["\\ADDR"];
+ RTLIL::SigSpec data = cell->connections["\\DATA"];
+ RTLIL::SigSpec en = cell->connections["\\EN"];
+
+ clk.extend(1, false);
+ clk_enable.extend(1, false);
+ clk_polarity.extend(1, false);
+ addr.extend(addr_bits, false);
+ data.extend(memory->width, false);
+ en.extend(1, false);
+
+ sig_wr_clk.append(clk);
+ sig_wr_clk_enable.append(clk_enable);
+ sig_wr_clk_polarity.append(clk_polarity);
+ sig_wr_addr.append(addr);
+ sig_wr_data.append(data);
+ sig_wr_en.append(en);
+ }
+
+ if (cell->type == "$memrd" && cell->parameters["\\MEMID"].str == memory->name)
+ {
+ rd_ports++;
+ del_cell_ids.push_back(cell->name);
+
+ RTLIL::SigSpec clk = cell->connections["\\CLK"];
+ RTLIL::SigSpec clk_enable = RTLIL::SigSpec(cell->parameters["\\CLK_ENABLE"]);
+ RTLIL::SigSpec clk_polarity = RTLIL::SigSpec(cell->parameters["\\CLK_POLARITY"]);
+ RTLIL::SigSpec addr = cell->connections["\\ADDR"];
+ RTLIL::SigSpec data = cell->connections["\\DATA"];
+
+ clk.extend(1, false);
+ clk_enable.extend(1, false);
+ clk_polarity.extend(1, false);
+ addr.extend(addr_bits, false);
+ data.extend(memory->width, false);
+
+ sig_rd_clk.append(clk);
+ sig_rd_clk_enable.append(clk_enable);
+ sig_rd_clk_polarity.append(clk_polarity);
+ sig_rd_addr.append(addr);
+ sig_rd_data.append(data);
+ }
+ }
+
+ std::stringstream sstr;
+ sstr << "$mem$" << memory->name << "$" << (RTLIL::autoidx++);
+
+ RTLIL::Cell *mem = new RTLIL::Cell;
+ mem->name = sstr.str();
+ mem->type = "$mem";
+
+ mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);
+ mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
+ mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
+ mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
+ mem->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
+
+ sig_wr_clk_enable.optimize();
+ sig_wr_clk_polarity.optimize();
+
+ assert(sig_wr_clk.width == wr_ports);
+ assert(sig_wr_clk_enable.width == wr_ports && sig_wr_clk_enable.is_fully_const());
+ assert(sig_wr_clk_polarity.width == wr_ports && sig_wr_clk_polarity.is_fully_const());
+ assert(sig_wr_addr.width == wr_ports * addr_bits);
+ assert(sig_wr_data.width == wr_ports * memory->width);
+ assert(sig_wr_en.width == wr_ports);
+
+ mem->parameters["\\WR_PORTS"] = RTLIL::Const(wr_ports);
+ mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
+
+ mem->connections["\\WR_CLK"] = sig_wr_clk;
+ mem->connections["\\WR_ADDR"] = sig_wr_addr;
+ mem->connections["\\WR_DATA"] = sig_wr_data;
+ mem->connections["\\WR_EN"] = sig_wr_en;
+
+ sig_rd_clk_enable.optimize();
+ sig_rd_clk_polarity.optimize();
+
+ assert(sig_rd_clk.width == rd_ports);
+ assert(sig_rd_clk_enable.width == rd_ports && sig_rd_clk_enable.is_fully_const());
+ assert(sig_rd_clk_polarity.width == rd_ports && sig_rd_clk_polarity.is_fully_const());
+ assert(sig_rd_addr.width == rd_ports * addr_bits);
+ assert(sig_rd_data.width == rd_ports * memory->width);
+
+ mem->parameters["\\RD_PORTS"] = RTLIL::Const(rd_ports);
+ mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
+ mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_enable.chunks[0].data : RTLIL::Const(0, 0);
+
+ mem->connections["\\RD_CLK"] = sig_rd_clk;
+ mem->connections["\\RD_ADDR"] = sig_rd_addr;
+ mem->connections["\\RD_DATA"] = sig_rd_data;
+
+ for (auto &id : del_cell_ids) {
+ delete module->cells[id];
+ module->cells.erase(id);
+ }
+ module->cells[mem->name] = mem;
+}
+
+static void handle_module(RTLIL::Module *module)
+{
+ for (auto &mem_it : module->memories) {
+ handle_memory(module, mem_it.second);
+ delete mem_it.second;
+ }
+ module->memories.clear();
+}
+
+struct MemoryCollectPass : public Pass {
+ MemoryCollectPass() : Pass("memory_collect") { }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+ log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
+ extra_args(args, 1, design);
+ for (auto &mod_it : design->modules)
+ handle_module(mod_it.second);
+ }
+} MemoryCollectPass;
+
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
new file mode 100644
index 00000000..e188a7af
--- /dev/null
+++ b/passes/memory/memory_dff.cc
@@ -0,0 +1,200 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <stdlib.h>
+#include <assert.h>
+#include <sstream>
+
+static void normalize_sig(RTLIL::Module *module, RTLIL::SigSpec &sig)
+{
+ for (auto &conn : module->connections)
+ sig.replace(conn.first, conn.second);
+}
+
+static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::SigSpec &clk, bool &clk_polarity, bool after = false)
+{
+ bool replaced_bits = false;
+ normalize_sig(module, sig);
+ sig.expand();
+
+ for (size_t i = 0; i < sig.chunks.size(); i++)
+ {
+ RTLIL::SigChunk &chunk = sig.chunks[i];
+
+ if (chunk.wire == NULL)
+ continue;
+
+ for (auto &cell_it : module->cells)
+ {
+ RTLIL::Cell *cell = cell_it.second;
+
+ if (cell->type != "$dff")
+ continue;
+
+ if (clk != RTLIL::SigSpec(RTLIL::State::Sx)) {
+ if (cell->connections["\\CLK"] != clk)
+ continue;
+ if (cell->parameters["\\CLK_POLARITY"].as_bool() != clk_polarity)
+ continue;
+ }
+
+ RTLIL::SigSpec q_norm = cell->connections[after ? "\\D" : "\\Q"];
+ normalize_sig(module, q_norm);
+
+ RTLIL::SigSpec d = q_norm.extract(chunk, &cell->connections[after ? "\\Q" : "\\D"]);
+ if (d.width != 1)
+ continue;
+
+ assert(d.chunks.size() == 1);
+ chunk = d.chunks[0];
+ clk = cell->connections["\\CLK"];
+ clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
+ replaced_bits = true;
+ goto replaced_this_bit;
+ }
+
+ return false;
+ replaced_this_bit:;
+ }
+
+ sig.optimize();
+ return replaced_bits;
+}
+
+static void handle_wr_cell(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
+
+ RTLIL::SigSpec clk = RTLIL::SigSpec(RTLIL::State::Sx);
+ bool clk_polarity = 0;
+
+ RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
+ if (!find_sig_before_dff(module, sig_addr, clk, clk_polarity)) {
+ log("no (compatible) $dff for address input found.\n");
+ return;
+ }
+
+ RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
+ if (!find_sig_before_dff(module, sig_data, clk, clk_polarity)) {
+ log("no (compatible) $dff for data input found.\n");
+ return;
+ }
+
+ RTLIL::SigSpec sig_en = cell->connections["\\EN"];
+ if (!find_sig_before_dff(module, sig_en, clk, clk_polarity)) {
+ log("no (compatible) $dff for enable input found.\n");
+ return;
+ }
+
+ cell->connections["\\CLK"] = clk;
+ cell->connections["\\ADDR"] = sig_addr;
+ cell->connections["\\DATA"] = sig_data;
+ cell->connections["\\EN"] = sig_en;
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ log("merged $dff to cell.\n");
+}
+
+#if 1
+static void handle_rd_cell(RTLIL::Module*, RTLIL::Cell*)
+{
+ // merging dffs into read ports isn't neccessary for memory_map.
+ // we'd loose the information if the register is on the address or
+ // data port and wouldn't get any benefits.
+}
+#else
+static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig)
+{
+ normalize_sig(module, sig);
+ sig.sort_and_unify();
+
+ std::stringstream sstr;
+ sstr << "$memory_dff_disconnected$" << (RTLIL::autoidx++);
+
+ RTLIL::Wire *wire = new RTLIL::Wire;
+ wire->name = sstr.str();
+ wire->width = sig.width;
+ module->wires[wire->name] = wire;
+
+ RTLIL::SigSpec newsig(wire);
+
+ for (auto &cell_it : module->cells) {
+ RTLIL::Cell *cell = cell_it.second;
+ if (cell->type == "$dff")
+ cell->connections["\\Q"].replace(sig, newsig);
+ }
+}
+
+static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ log("Checking cell `%s' in module `%s': ", cell->name.c_str(), module->name.c_str());
+
+ bool clk_polarity = 0;
+
+ RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
+ RTLIL::SigSpec sig_addr = cell->connections["\\ADDR"];
+ if (find_sig_before_dff(module, sig_addr, clk_addr, clk_polarity))
+ {
+ cell->connections["\\CLK"] = clk_addr;
+ cell->connections["\\ADDR"] = sig_addr;
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ log("merged address $dff to cell.\n");
+ return;
+ }
+
+ RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
+ RTLIL::SigSpec sig_data = cell->connections["\\DATA"];
+ if (find_sig_before_dff(module, sig_data, clk_data, clk_polarity, true))
+ {
+ disconnect_dff(module, sig_data);
+ cell->connections["\\CLK"] = clk_data;
+ cell->connections["\\DATA"] = sig_data;
+ cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1);
+ cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity);
+ log("merged data $dff to cell.\n");
+ return;
+ }
+
+ log("no (compatible) $dff found.\n");
+}
+#endif
+
+static void handle_module(RTLIL::Module *module)
+{
+ for (auto &cell_it : module->cells) {
+ if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
+ handle_wr_cell(module, cell_it.second);
+ if (cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
+ handle_rd_cell(module, cell_it.second);
+ }
+}
+
+struct MemoryDffPass : public Pass {
+ MemoryDffPass() : Pass("memory_dff") { }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+ log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
+ extra_args(args, 1, design);
+ for (auto &mod_it : design->modules)
+ handle_module(mod_it.second);
+ }
+} MemoryDffPass;
+
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
new file mode 100644
index 00000000..e7783083
--- /dev/null
+++ b/passes/memory/memory_map.cc
@@ -0,0 +1,334 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/register.h"
+#include "kernel/log.h"
+#include <sstream>
+#include <set>
+#include <stdlib.h>
+#include <assert.h>
+
+static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
+{
+ std::stringstream sstr;
+ sstr << "$memory" << name << token1;
+
+ if (i >= 0)
+ sstr << "[" << i << "]";
+
+ sstr << token2;
+
+ if (j >= 0)
+ sstr << "[" << j << "]";
+
+ sstr << token3;
+
+ if (k >= 0)
+ sstr << "[" << k << "]";
+
+ sstr << token4 << "$" << (RTLIL::autoidx++);
+ return sstr.str();
+}
+
+static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ std::set<int> static_ports;
+ std::map<int, RTLIL::SigSpec> static_cells_map;
+ int mem_size = cell->parameters["\\SIZE"].as_int();
+ int mem_width = cell->parameters["\\WIDTH"].as_int();
+ int mem_offset = cell->parameters["\\OFFSET"].as_int();
+ int mem_abits = cell->parameters["\\ABITS"].as_int();
+
+ // delete unused memory cell
+ if (cell->parameters["\\RD_PORTS"].as_int() == 0 && cell->parameters["\\WR_PORTS"].as_int() == 0) {
+ module->cells.erase(cell->name);
+ delete cell;
+ return;
+ }
+
+ // all write ports must share the same clock
+ RTLIL::SigSpec clocks = cell->connections["\\WR_CLK"];
+ RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
+ RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
+ RTLIL::SigSpec refclock;
+ RTLIL::State refclock_pol = RTLIL::State::Sx;
+ for (int i = 0; i < clocks.width; i++) {
+ RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(i, 1);
+ if (wr_en.is_fully_const() && wr_en.as_int() == 0) {
+ static_ports.insert(i);
+ continue;
+ }
+ if (clocks_en.bits[i] != RTLIL::State::S1) {
+ RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(i*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(i*mem_width, mem_width);
+ if (wr_addr.is_fully_const()) {
+ // FIXME: Actually we should check for wr_en.is_fully_const() also and
+ // create a $adff cell with this ports wr_en input as reset pin when wr_en
+ // is not a simple static 1.
+ static_cells_map[wr_addr.as_int()] = wr_data;
+ static_ports.insert(i);
+ continue;
+ }
+ log("Not mapping memory cell %s in module %s (write port %d has no clock).\n",
+ cell->name.c_str(), module->name.c_str(), i);
+ return;
+ }
+ if (refclock.width == 0) {
+ refclock = clocks.extract(i, 1);
+ refclock_pol = clocks_pol.bits[i];
+ }
+ if (clocks.extract(i, 1) != refclock || clocks_pol.bits[i] != refclock_pol) {
+ log("Not mapping memory cell %s in module %s (write clock %d is incompatible with other clocks).\n",
+ cell->name.c_str(), module->name.c_str(), i);
+ return;
+ }
+ }
+
+ log("Mapping memory cell %s in module %s:\n", cell->name.c_str(), module->name.c_str());
+
+ std::vector<RTLIL::SigSpec> data_reg_in;
+ std::vector<RTLIL::SigSpec> data_reg_out;
+
+ int count_static = 0;
+
+ for (int i = 0; i < mem_size; i++)
+ {
+ if (static_cells_map.count(i) > 0)
+ {
+ data_reg_in.push_back(RTLIL::SigSpec(RTLIL::State::Sz, mem_width));
+ data_reg_out.push_back(static_cells_map[i]);
+ count_static++;
+ }
+ else
+ {
+ RTLIL::Cell *c = new RTLIL::Cell;
+ c->name = genid(cell->name, "", i);
+ c->type = "$dff";
+ c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
+ c->connections["\\CLK"] = clocks.extract(0, 1);
+ module->cells[c->name] = c;
+
+ RTLIL::Wire *w_in = new RTLIL::Wire;
+ w_in->name = genid(cell->name, "", i, "$d");
+ w_in->width = mem_width;
+ module->wires[w_in->name] = w_in;
+ data_reg_in.push_back(RTLIL::SigSpec(w_in));
+ c->connections["\\D"] = data_reg_in.back();
+
+ RTLIL::Wire *w_out = new RTLIL::Wire;
+ w_out->name = stringf("%s[%d]", cell->parameters["\\MEMID"].str.c_str(), i);
+ if (module->wires.count(w_out->name) > 0)
+ w_out->name = genid(cell->name, "", i, "$q");
+ w_out->width = mem_width;
+ w_out->start_offset = mem_offset;
+ module->wires[w_out->name] = w_out;
+ data_reg_out.push_back(RTLIL::SigSpec(w_out));
+ c->connections["\\Q"] = data_reg_out.back();
+ }
+ }
+
+ log(" created %d $dff cells and %d static cells of width %d.\n", mem_size-count_static, count_static, mem_width);
+
+ int count_dff = 0, count_mux = 0, count_wrmux = 0;
+
+ for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
+ {
+ RTLIL::SigSpec rd_addr = cell->connections["\\RD_ADDR"].extract(i*mem_abits, mem_abits);
+
+ std::vector<RTLIL::SigSpec> rd_signals;
+ rd_signals.push_back(cell->connections["\\RD_DATA"].extract(i*mem_width, mem_width));
+
+ if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
+ {
+#if 1
+ RTLIL::Cell *c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$rdreg", i);
+ c->type = "$dff";
+ c->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
+ c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
+ c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
+ c->connections["\\D"] = rd_addr;
+ module->cells[c->name] = c;
+ count_dff++;
+
+ RTLIL::Wire *w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$rdreg", i, "$q");
+ w->width = mem_abits;
+ module->wires[w->name] = w;
+
+ c->connections["\\Q"] = RTLIL::SigSpec(w);
+ rd_addr = RTLIL::SigSpec(w);
+#else
+ RTLIL::Cell *c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$rdreg", i);
+ c->type = "$dff";
+ c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ c->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
+ c->connections["\\CLK"] = cell->connections["\\RD_CLK"].extract(i, 1);
+ c->connections["\\Q"] = rd_signals.back();
+ module->cells[c->name] = c;
+ count_dff++;
+
+ RTLIL::Wire *w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$rdreg", i, "$d");
+ w->width = mem_width;
+ module->wires[w->name] = w;
+
+ rd_signals.clear();
+ rd_signals.push_back(RTLIL::SigSpec(w));
+ c->connections["\\D"] = rd_signals.back();
+#endif
+ }
+
+ for (int j = 0; j < mem_abits; j++)
+ {
+ std::vector<RTLIL::SigSpec> next_rd_signals;
+
+ for (size_t k = 0; k < rd_signals.size(); k++)
+ {
+ RTLIL::Cell *c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$rdmux", i, "", j, "", k);
+ c->type = "$mux";
+ c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ c->connections["\\Y"] = rd_signals[k];
+ c->connections["\\S"] = rd_addr.extract(mem_abits-j-1, 1);
+ module->cells[c->name] = c;
+ count_mux++;
+
+ RTLIL::Wire *w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$a");
+ w->width = mem_width;
+ module->wires[w->name] = w;
+ c->connections["\\A"] = RTLIL::SigSpec(w);
+
+ w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$rdmux", i, "", j, "", k, "$b");
+ w->width = mem_width;
+ module->wires[w->name] = w;
+ c->connections["\\B"] = RTLIL::SigSpec(w);
+
+ next_rd_signals.push_back(c->connections["\\A"]);
+ next_rd_signals.push_back(c->connections["\\B"]);
+ }
+
+ next_rd_signals.swap(rd_signals);
+ }
+
+ for (int j = 0; j < mem_size; j++)
+ module->connections.push_back(RTLIL::SigSig(rd_signals[j], data_reg_out[j]));
+ }
+
+ log(" read interface: %d $dff and %d $mux cells.\n", count_dff, count_mux);
+
+ for (int i = 0; i < mem_size; i++)
+ {
+ if (static_cells_map.count(i) > 0)
+ continue;
+
+ RTLIL::SigSpec sig = data_reg_out[i];
+
+ for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
+ {
+ RTLIL::SigSpec wr_addr = cell->connections["\\WR_ADDR"].extract(j*mem_abits, mem_abits);
+ RTLIL::SigSpec wr_data = cell->connections["\\WR_DATA"].extract(j*mem_width, mem_width);
+ RTLIL::SigSpec wr_en = cell->connections["\\WR_EN"].extract(j, 1);
+
+ RTLIL::Cell *c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$wreq", i, "", j);
+ c->type = "$eq";
+ c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
+ c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
+ c->parameters["\\A_WIDTH"] = cell->parameters["\\ABITS"];
+ c->parameters["\\B_WIDTH"] = cell->parameters["\\ABITS"];
+ c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ c->connections["\\A"] = RTLIL::SigSpec(i, mem_abits);
+ c->connections["\\B"] = wr_addr;
+ module->cells[c->name] = c;
+ count_wrmux++;
+
+ RTLIL::Wire *w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$wreq", i, "", j, "$y");
+ module->wires[w->name] = w;
+ c->connections["\\Y"] = RTLIL::SigSpec(w);
+
+ c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$wren", i, "", j);
+ c->type = "$and";
+ c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
+ c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
+ c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
+ c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
+ c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
+ c->connections["\\A"] = RTLIL::SigSpec(w);
+ c->connections["\\B"] = wr_en;
+ module->cells[c->name] = c;
+
+ w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$wren", i, "", j, "$y");
+ module->wires[w->name] = w;
+ c->connections["\\Y"] = RTLIL::SigSpec(w);
+
+ c = new RTLIL::Cell;
+ c->name = genid(cell->name, "$wrmux", i, "", j);
+ c->type = "$mux";
+ c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
+ c->connections["\\A"] = sig;
+ c->connections["\\B"] = wr_data;
+ c->connections["\\S"] = RTLIL::SigSpec(w);
+ module->cells[c->name] = c;
+
+ w = new RTLIL::Wire;
+ w->name = genid(cell->name, "$wrmux", i, "", j, "$y");
+ w->width = mem_width;
+ module->wires[w->name] = w;
+ c->connections["\\Y"] = RTLIL::SigSpec(w);
+ sig = RTLIL::SigSpec(w);
+ }
+
+ module->connections.push_back(RTLIL::SigSig(data_reg_in[i], sig));
+ }
+
+ log(" write interface: %d blocks of $eq, $and and $mux cells.\n", count_wrmux);
+
+ module->cells.erase(cell->name);
+ delete cell;
+ return;
+}
+
+static void handle_module(RTLIL::Module *module)
+{
+ std::vector<RTLIL::Cell*> cells;
+ for (auto &it : module->cells)
+ if (it.second->type == "$mem")
+ cells.push_back(it.second);
+ for (auto cell : cells)
+ handle_cell(module, cell);
+}
+
+struct MemoryMapPass : public Pass {
+ MemoryMapPass() : Pass("memory_map") { }
+ virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
+ log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
+ extra_args(args, 1, design);
+ for (auto &mod_it : design->modules)
+ handle_module(mod_it.second);
+ }
+} MemoryMapPass;
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-25 03:32:35 +0000