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-rw-r--r--passes/opt/opt_clean.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index dbe1804e..183d6757 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -35,7 +35,7 @@ static int count_rm_cells, count_rm_wires;
static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
{
SigMap assign_map(module);
- std::set<RTLIL::Cell*> queue, unused;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused;
SigSet<RTLIL::Cell*> wire2driver;
for (auto &it : module->cells) {
@@ -66,7 +66,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
while (queue.size() > 0)
{
- std::set<RTLIL::Cell*> new_queue;
+ std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> new_queue;
for (auto cell : queue)
unused.erase(cell);
for (auto cell : queue) {