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-rw-r--r--passes/opt/opt_clean.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 0e5ed238..15bbf54e 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -293,6 +293,19 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose)
if (verbose)
log("Finding unused cells or wires in module %s..\n", module->name.c_str());
+ std::vector<RTLIL::Cell*> delcells;
+ for (auto cell : module->cells())
+ if (cell->type == "$pos") {
+ bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
+ RTLIL::SigSpec a = cell->getPort("\\A");
+ RTLIL::SigSpec y = cell->getPort("\\Y");
+ a.extend_u0(SIZE(y), is_signed);
+ module->connect(y, a);
+ delcells.push_back(cell);
+ }
+ for (auto cell : delcells)
+ module->remove(cell);
+
rmunused_module_cells(module, verbose);
rmunused_module_signals(module, purge_mode, verbose);
}