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-rw-r--r--passes/opt/opt.cc25
-rw-r--r--passes/opt/opt_const.cc21
-rw-r--r--passes/opt/opt_muxtree.cc22
-rw-r--r--passes/opt/opt_reduce.cc17
-rw-r--r--passes/opt/opt_rmdff.cc17
-rw-r--r--passes/opt/opt_rmunused.cc21
-rw-r--r--passes/opt/opt_share.cc15
7 files changed, 127 insertions, 11 deletions
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index 9e33f78c..b742a095 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -26,7 +26,30 @@
bool OPT_DID_SOMETHING;
struct OptPass : public Pass {
- OptPass() : Pass("opt") { }
+ OptPass() : Pass("opt", "perform simple optimizations") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt [selection]\n");
+ log("\n");
+ log("This pass calls all the other opt_* passes in a useful manner. This performs\n");
+ log("a series of trivial optimizations and cleanups. This pass executes the other\n");
+ log("passes in the following order:\n");
+ log("\n");
+ log(" opt_const\n");
+ log(" opt_share -nomux\n");
+ log("\n");
+ log(" do\n");
+ log(" opt_muxtree\n");
+ log(" opt_reduce\n");
+ log(" opt_share\n");
+ log(" opt_rmdff\n");
+ log(" opt_rmunused\n");
+ log(" opt_const\n");
+ log(" while [changed design]\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT pass (performing simple optimizations).\n");
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 84b52544..4d00807a 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -44,14 +44,18 @@ void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string info, st
did_something = true;
}
-void replace_const_cells(RTLIL::Module *module)
+void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module)
{
+ if (!design->selected(module))
+ return;
+
SigMap assign_map(module);
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size());
for (auto &cell_it : module->cells)
- cells.push_back(cell_it.second);
+ if (design->selected(module, cell_it.second))
+ cells.push_back(cell_it.second);
for (auto cell : cells)
{
@@ -249,7 +253,16 @@ void replace_const_cells(RTLIL::Module *module)
}
struct OptConstPass : public Pass {
- OptConstPass() : Pass("opt_const") { }
+ OptConstPass() : Pass("opt_const", "perform const folding") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_const [selection]\n");
+ log("\n");
+ log("This pass performs const folding on internal cell types with constant inputs.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_CONST pass (perform const folding).\n");
@@ -260,7 +273,7 @@ struct OptConstPass : public Pass {
for (auto &mod_it : design->modules)
do {
did_something = false;
- replace_const_cells(mod_it.second);
+ replace_const_cells(design, mod_it.second);
} while (did_something);
log_pop();
diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc
index d1f4e7b1..9d622d6a 100644
--- a/passes/opt/opt_muxtree.cc
+++ b/passes/opt/opt_muxtree.cc
@@ -396,7 +396,20 @@ struct OptMuxtreeWorker
};
struct OptMuxtreePass : public Pass {
- OptMuxtreePass() : Pass("opt_muxtree") { }
+ OptMuxtreePass() : Pass("opt_muxtree", "eliminate dead trees in multiplexer trees") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_muxtree [selection]\n");
+ log("\n");
+ log("This pass analyzes the control signals for the multiplexer trees in the design\n");
+ log("and identifies inputs that can never be active. In then removes this dead\n");
+ log("branches from the multiplexer trees.\n");
+ log("\n");
+ log("This pass only operates on completely selected modules without processes.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_MUXTREE pass (detect dead branches in mux trees).\n");
@@ -404,8 +417,13 @@ struct OptMuxtreePass : public Pass {
int total_count = 0;
for (auto &mod_it : design->modules) {
+ if (!design->selected_whole_module(mod_it.first)) {
+ if (design->selected(mod_it.second))
+ log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
+ continue;
+ }
if (mod_it.second->processes.size() > 0) {
- log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
+ log("Skipping module %s as it contains processes.\n", id2cstr(mod_it.second->name));
} else {
OptMuxtreeWorker worker(design, mod_it.second);
total_count += worker.removed_count;
diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index deb4cc2c..98351762 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -216,7 +216,22 @@ struct OptReduceWorker
};
struct OptReducePass : public Pass {
- OptReducePass() : Pass("opt_reduce") { }
+ OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_reduce [selection]\n");
+ log("\n");
+ log("This pass performs two interlinked optimizations:\n");
+ log("\n");
+ log("1. it consolidates trees of large AND gates or OR gates and eliminates\n");
+ log("duplicated inputs.\n");
+ log("\n");
+ log("2. it identifies duplicated inputs to MUXes and replaces them with a single\n");
+ log("input with the original control signals OR'ed together.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index 384a4d85..4870f76b 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -93,7 +93,17 @@ delete_dff:
}
struct OptRmdffPass : public Pass {
- OptRmdffPass() : Pass("opt_rmdff") { }
+ OptRmdffPass() : Pass("opt_rmdff", "remove DFFs with constant inputs") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_rmdff [selection]\n");
+ log("\n");
+ log("This pass identifies flip-flops with constant inputs and replaces them with\n");
+ log("a constant driver.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
int total_count = 0;
@@ -103,10 +113,15 @@ struct OptRmdffPass : public Pass {
for (auto &mod_it : design->modules)
{
+ if (!design->selected(mod_it.second))
+ continue;
+
assign_map.set(mod_it.second);
std::vector<std::string> dff_list;
for (auto &it : mod_it.second->cells) {
+ if (!design->selected(mod_it.second, it.second))
+ continue;
if (it.second->type == "$_DFF_N_") dff_list.push_back(it.first);
if (it.second->type == "$_DFF_P_") dff_list.push_back(it.first);
if (it.second->type == "$_DFF_NN0_") dff_list.push_back(it.first);
diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc
index 33c09f28..9b276644 100644
--- a/passes/opt/opt_rmunused.cc
+++ b/passes/opt/opt_rmunused.cc
@@ -221,7 +221,21 @@ static void rmunused_module(RTLIL::Module *module)
}
struct OptRmUnusedPass : public Pass {
- OptRmUnusedPass() : Pass("opt_rmunused") { }
+ OptRmUnusedPass() : Pass("opt_rmunused", "remove unused cells and wires") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_rmunused [selection]\n");
+ log("\n");
+ log("This pass identifies wires and cells that are unused and removes them. Other\n");
+ log("often remove cells but leave the wires in the design or reconnect the wires\n");
+ log("but leave the old cells in the design. This pass can be used to clean up after\n");
+ log("the passes that do the actual work.\n");
+ log("\n");
+ log("This pass only operates on completely selected modules without processes.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_RMUNUSED pass (remove unused cells and wires).\n");
@@ -235,6 +249,11 @@ struct OptRmUnusedPass : public Pass {
ct.setup_stdcells_mem();
for (auto &mod_it : design->modules) {
+ if (!design->selected_whole_module(mod_it.first)) {
+ if (design->selected(mod_it.second))
+ log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name));
+ continue;
+ }
if (mod_it.second->processes.size() > 0) {
log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
} else {
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 71822b11..9f79d060 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -218,7 +218,20 @@ struct OptShareWorker
};
struct OptSharePass : public Pass {
- OptSharePass() : Pass("opt_share") { }
+ OptSharePass() : Pass("opt_share", "consolidate identical cells") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" opt_share [-nomux] [selection]\n");
+ log("\n");
+ log("This pass identifies cells with identical type and input signals. Such cells\n");
+ log("are then merged to one cell.\n");
+ log("\n");
+ log(" -nomux\n");
+ log(" Do not merge MUX cells.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing OPT_SHARE pass (detect identical cells).\n");
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 10:44:17 +0000