diff options
Diffstat (limited to 'passes/opt')
-rw-r--r-- | passes/opt/opt_clean.cc | 8 | ||||
-rw-r--r-- | passes/opt/opt_const.cc | 28 | ||||
-rw-r--r-- | passes/opt/share.cc | 106 | ||||
-rw-r--r-- | passes/opt/wreduce.cc | 84 |
4 files changed, 113 insertions, 113 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 004a2078..c0b8853a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -229,9 +229,9 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { maybe_del_wires.push_back(wire); } else { - log_assert(SIZE(s1) == SIZE(s2)); + log_assert(GetSize(s1) == GetSize(s2)); RTLIL::SigSig new_conn; - for (int i = 0; i < SIZE(s1); i++) + for (int i = 0; i < GetSize(s1); i++) if (s1[i] != s2[i]) { new_conn.first.append_bit(s1[i]); new_conn.second.append_bit(s2[i]); @@ -250,7 +250,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire)); if (!used_signals_nodrivers.check_any(sig)) { std::string unused_bits; - for (int i = 0; i < SIZE(sig); i++) { + for (int i = 0; i < GetSize(sig); i++) { if (sig[i].wire == NULL) continue; if (!used_signals_nodrivers.check(sig[i])) { @@ -299,7 +299,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose) bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool(); RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec y = cell->getPort("\\Y"); - a.extend_u0(SIZE(y), is_signed); + a.extend_u0(GetSize(y), is_signed); module->connect(y, a); delcells.push_back(cell); } diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 7c9fca96..c726c7b3 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -107,7 +107,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_N }; std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::set<RTLIL::SigBit>> grouped_bits[GRP_N]; - for (int i = 0; i < SIZE(bits_y); i++) + for (int i = 0; i < GetSize(bits_y); i++) { int group_idx = GRP_DYN; RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i]; @@ -131,7 +131,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ } for (int i = 0; i < GRP_N; i++) - if (SIZE(grouped_bits[i]) == SIZE(bits_y)) + if (GetSize(grouped_bits[i]) == GetSize(bits_y)) return false; log("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n", @@ -142,7 +142,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ if (grouped_bits[i].empty()) continue; - RTLIL::Wire *new_y = module->addWire(NEW_ID, SIZE(grouped_bits[i])); + RTLIL::Wire *new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i])); RTLIL::SigSpec new_a, new_b; RTLIL::SigSig new_conn; @@ -486,8 +486,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec new_a, new_b; - log_assert(SIZE(a) == SIZE(b)); - for (int i = 0; i < SIZE(a); i++) { + log_assert(GetSize(a) == GetSize(b)); + for (int i = 0; i < GetSize(a); i++) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1); @@ -559,15 +559,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int()); - if (SIZE(sig_a) < SIZE(sig_y)) - sig_a.extend(SIZE(sig_y), cell->getParam("\\A_SIGNED").as_bool()); + if (GetSize(sig_a) < GetSize(sig_y)) + sig_a.extend(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); - for (int i = 0; i < SIZE(sig_y); i++) { + for (int i = 0; i < GetSize(sig_y); i++) { int idx = i + shift_bits; - if (0 <= idx && idx < SIZE(sig_a)) + if (0 <= idx && idx < GetSize(sig_a)) sig_y[i] = sig_a[idx]; - else if (SIZE(sig_a) <= idx && sign_ext) - sig_y[i] = sig_a[SIZE(sig_a)-1]; + else if (GetSize(sig_a) <= idx && sign_ext) + sig_y[i] = sig_a[GetSize(sig_a)-1]; } cover_list("opt.opt_const.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str()); @@ -754,7 +754,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons if (cell->getPort("\\S").size() != new_s.size()) { cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str()); log("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n", - SIZE(cell->getPort("\\S")) - SIZE(new_s), log_id(cell->type), log_id(cell), log_id(module)); + GetSize(cell->getPort("\\S")) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module)); cell->setPort("\\A", new_a); cell->setPort("\\B", new_b); cell->setPort("\\S", new_s); @@ -900,11 +900,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6); - while (SIZE(new_b) > 1 && new_b.back() == RTLIL::State::S0) + while (GetSize(new_b) > 1 && new_b.back() == RTLIL::State::S0) new_b.pop_back(); cell->type = "$shl"; - cell->parameters["\\B_WIDTH"] = SIZE(new_b); + cell->parameters["\\B_WIDTH"] = GetSize(new_b); cell->parameters["\\B_SIGNED"] = false; cell->setPort("\\B", new_b); cell->check(); diff --git a/passes/opt/share.cc b/passes/opt/share.cc index 44374482..35458693 100644 --- a/passes/opt/share.cc +++ b/passes/opt/share.cc @@ -109,14 +109,14 @@ struct ShareWorker static int bits_macc_port(const Macc::port_t &p, int width) { - if (SIZE(p.in_a) == 0 || SIZE(p.in_b) == 0) - return std::min(std::max(SIZE(p.in_a), SIZE(p.in_b)), width); - return std::min(SIZE(p.in_a), width) * std::min(SIZE(p.in_b), width) / 2; + if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0) + return std::min(std::max(GetSize(p.in_a), GetSize(p.in_b)), width); + return std::min(GetSize(p.in_a), width) * std::min(GetSize(p.in_b), width) / 2; } static int bits_macc(const Macc &m, int width) { - int bits = SIZE(m.bit_ports); + int bits = GetSize(m.bit_ports); for (auto &p : m.ports) bits += bits_macc_port(p, width); return bits; @@ -125,17 +125,17 @@ struct ShareWorker static int bits_macc(RTLIL::Cell *c) { Macc m(c); - int width = SIZE(c->getPort("\\Y")); + int width = GetSize(c->getPort("\\Y")); return bits_macc(m, width); } static bool cmp_macc_ports(const Macc::port_t &p1, const Macc::port_t &p2) { - bool mul1 = SIZE(p1.in_a) && SIZE(p1.in_b); - bool mul2 = SIZE(p2.in_a) && SIZE(p2.in_b); + bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b); + bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b); - int w1 = mul1 ? SIZE(p1.in_a) * SIZE(p1.in_b) : SIZE(p1.in_a) + SIZE(p1.in_b); - int w2 = mul2 ? SIZE(p2.in_a) * SIZE(p2.in_b) : SIZE(p2.in_a) + SIZE(p2.in_b); + int w1 = mul1 ? GetSize(p1.in_a) * GetSize(p1.in_b) : GetSize(p1.in_a) + GetSize(p1.in_b); + int w2 = mul2 ? GetSize(p2.in_a) * GetSize(p2.in_b) : GetSize(p2.in_a) + GetSize(p2.in_b); if (mul1 != mul2) return mul1; @@ -164,22 +164,22 @@ struct ShareWorker if (p1.do_subtract != p2.do_subtract) return -1; - bool mul1 = SIZE(p1.in_a) && SIZE(p1.in_b); - bool mul2 = SIZE(p2.in_a) && SIZE(p2.in_b); + bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b); + bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b); if (mul1 != mul2) return -1; bool force_signed = false, force_not_signed = false; - if ((SIZE(p1.in_a) && SIZE(p1.in_a) < w1) || (SIZE(p1.in_b) && SIZE(p1.in_b) < w1)) { + if ((GetSize(p1.in_a) && GetSize(p1.in_a) < w1) || (GetSize(p1.in_b) && GetSize(p1.in_b) < w1)) { if (p1.is_signed) force_signed = true; else force_not_signed = true; } - if ((SIZE(p2.in_a) && SIZE(p2.in_a) < w2) || (SIZE(p2.in_b) && SIZE(p2.in_b) < w2)) { + if ((GetSize(p2.in_a) && GetSize(p2.in_a) < w2) || (GetSize(p2.in_b) && GetSize(p2.in_b) < w2)) { if (p2.is_signed) force_signed = true; else @@ -194,22 +194,22 @@ struct ShareWorker RTLIL::SigSpec sig_a1 = p1.in_a, sig_b1 = p1.in_b; RTLIL::SigSpec sig_a2 = p2.in_a, sig_b2 = p2.in_b; - RTLIL::SigSpec sig_a = SIZE(sig_a1) > SIZE(sig_a2) ? sig_a1 : sig_a2; - RTLIL::SigSpec sig_b = SIZE(sig_b1) > SIZE(sig_b2) ? sig_b1 : sig_b2; + RTLIL::SigSpec sig_a = GetSize(sig_a1) > GetSize(sig_a2) ? sig_a1 : sig_a2; + RTLIL::SigSpec sig_b = GetSize(sig_b1) > GetSize(sig_b2) ? sig_b1 : sig_b2; - sig_a1.extend_u0(SIZE(sig_a), p1.is_signed); - sig_b1.extend_u0(SIZE(sig_b), p1.is_signed); + sig_a1.extend_u0(GetSize(sig_a), p1.is_signed); + sig_b1.extend_u0(GetSize(sig_b), p1.is_signed); - sig_a2.extend_u0(SIZE(sig_a), p2.is_signed); - sig_b2.extend_u0(SIZE(sig_b), p2.is_signed); + sig_a2.extend_u0(GetSize(sig_a), p2.is_signed); + sig_b2.extend_u0(GetSize(sig_b), p2.is_signed); - if (supercell_aux && SIZE(sig_a)) { - sig_a = module->addWire(NEW_ID, SIZE(sig_a)); + if (supercell_aux && GetSize(sig_a)) { + sig_a = module->addWire(NEW_ID, GetSize(sig_a)); supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a)); } - if (supercell_aux && SIZE(sig_b)) { - sig_b = module->addWire(NEW_ID, SIZE(sig_b)); + if (supercell_aux && GetSize(sig_b)) { + sig_b = module->addWire(NEW_ID, GetSize(sig_b)); supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b)); } @@ -221,13 +221,13 @@ struct ShareWorker supermacc->ports.push_back(p); } - int score = 1000 + abs(SIZE(p1.in_a) - SIZE(p2.in_a)) * std::max(abs(SIZE(p1.in_b) - SIZE(p2.in_b)), 1); + int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * std::max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1); - for (int i = 0; i < std::min(SIZE(p1.in_a), SIZE(p2.in_a)); i++) + for (int i = 0; i < std::min(GetSize(p1.in_a), GetSize(p2.in_a)); i++) if (p1.in_a[i] == p2.in_a[i] && score > 0) score--; - for (int i = 0; i < std::min(SIZE(p1.in_b), SIZE(p2.in_b)); i++) + for (int i = 0; i < std::min(GetSize(p1.in_b), GetSize(p2.in_b)); i++) if (p1.in_b[i] == p2.in_b[i] && score > 0) score--; @@ -239,7 +239,7 @@ struct ShareWorker { Macc m1(c1), m2(c2), supermacc; - int w1 = SIZE(c1->getPort("\\Y")), w2 = SIZE(c2->getPort("\\Y")); + int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y")); int width = std::max(w1, w2); m1.optimize(w1); @@ -250,10 +250,10 @@ struct ShareWorker std::set<int> m1_unmapped, m2_unmapped; - for (int i = 0; i < SIZE(m1.ports); i++) + for (int i = 0; i < GetSize(m1.ports); i++) m1_unmapped.insert(i); - for (int i = 0; i < SIZE(m2.ports); i++) + for (int i = 0; i < GetSize(m2.ports); i++) m2_unmapped.insert(i); while (1) @@ -280,14 +280,14 @@ struct ShareWorker RTLIL::SigSpec sig_a = m1.ports[i].in_a; RTLIL::SigSpec sig_b = m1.ports[i].in_b; - if (supercell_aux && SIZE(sig_a)) { - sig_a = module->addWire(NEW_ID, SIZE(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, SIZE(sig_a)), m1.ports[i].in_a, act, sig_a)); + if (supercell_aux && GetSize(sig_a)) { + sig_a = module->addWire(NEW_ID, GetSize(sig_a)); + supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.ports[i].in_a, act, sig_a)); } - if (supercell_aux && SIZE(sig_b)) { - sig_b = module->addWire(NEW_ID, SIZE(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, SIZE(sig_b)), m1.ports[i].in_b, act, sig_b)); + if (supercell_aux && GetSize(sig_b)) { + sig_b = module->addWire(NEW_ID, GetSize(sig_b)); + supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.ports[i].in_b, act, sig_b)); } Macc::port_t p; @@ -303,14 +303,14 @@ struct ShareWorker RTLIL::SigSpec sig_a = m2.ports[i].in_a; RTLIL::SigSpec sig_b = m2.ports[i].in_b; - if (supercell_aux && SIZE(sig_a)) { - sig_a = module->addWire(NEW_ID, SIZE(sig_a)); - supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_a, RTLIL::SigSpec(0, SIZE(sig_a)), act, sig_a)); + if (supercell_aux && GetSize(sig_a)) { + sig_a = module->addWire(NEW_ID, GetSize(sig_a)); + supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a)); } - if (supercell_aux && SIZE(sig_b)) { - sig_b = module->addWire(NEW_ID, SIZE(sig_b)); - supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_b, RTLIL::SigSpec(0, SIZE(sig_b)), act, sig_b)); + if (supercell_aux && GetSize(sig_b)) { + sig_b = module->addWire(NEW_ID, GetSize(sig_b)); + supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b)); } Macc::port_t p; @@ -765,7 +765,7 @@ struct ShareWorker std::map<RTLIL::SigBit, RTLIL::State> p_bits; std::vector<RTLIL::SigBit> p_first_bits = p.first; - for (int i = 0; i < SIZE(p_first_bits); i++) { + for (int i = 0; i < GetSize(p_first_bits); i++) { RTLIL::SigBit b = p_first_bits[i]; RTLIL::State v = p.second.bits[i]; if (p_bits.count(b) && p_bits.at(b) != v) @@ -837,13 +837,13 @@ struct ShareWorker if (cell_out_bits.count(bit)) used_in_a = true; - for (int i = 0; i < SIZE(sig_b); i++) + for (int i = 0; i < GetSize(sig_b); i++) if (cell_out_bits.count(sig_b[i])) used_in_b_parts.insert(i / width); if (used_in_a) for (auto p : c_patterns) { - for (int i = 0; i < SIZE(sig_s); i++) + for (int i = 0; i < GetSize(sig_s); i++) p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0); if (sort_check_activation_pattern(p)) activation_patterns_cache[cell].insert(p); @@ -899,7 +899,7 @@ struct ShareWorker std::vector<RTLIL::SigBit> p_first = p.first; std::pair<RTLIL::SigSpec, RTLIL::Const> new_p; - for (int i = 0; i < SIZE(p_first); i++) + for (int i = 0; i < GetSize(p_first); i++) if (filter_bits.count(p_first[i]) == 0) { new_p.first.append_bit(p_first[i]); new_p.second.bits.push_back(p.second.bits.at(i)); @@ -1078,7 +1078,7 @@ struct ShareWorker return; log("Found %d cells in module %s that may be considered for resource sharing.\n", - SIZE(shareable_cells), log_id(module)); + GetSize(shareable_cells), log_id(module)); for (auto cell : module->cells()) if (cell->type == "$pmux") @@ -1108,7 +1108,7 @@ struct ShareWorker continue; } - log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals)); + log(" Found %d activation_patterns using ctrl signal %s.\n", GetSize(cell_activation_patterns), log_signal(cell_activation_signals)); std::vector<RTLIL::Cell*> candidates; find_shareable_partners(candidates, cell); @@ -1118,7 +1118,7 @@ struct ShareWorker continue; } - log(" Found %d candidates:", SIZE(candidates)); + log(" Found %d candidates:", GetSize(candidates)); for (auto c : candidates) log(" %s", log_id(c)); log("\n"); @@ -1144,7 +1144,7 @@ struct ShareWorker } log(" Found %d activation_patterns using ctrl signal %s.\n", - SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals)); + GetSize(other_cell_activation_patterns), log_signal(other_cell_activation_signals)); const std::set<RTLIL::SigBit> &cell_forbidden_controls = find_forbidden_controls(cell); const std::set<RTLIL::SigBit> &other_cell_forbidden_controls = find_forbidden_controls(other_cell); @@ -1240,12 +1240,12 @@ struct ShareWorker ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active))); log(" Size of SAT problem: %d cells, %d variables, %d clauses\n", - SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses()); + GetSize(sat_cells), ez.numCnfVariables(), ez.numCnfClauses()); if (ez.solve(sat_model, sat_model_values)) { log(" According to the SAT solver this pair of cells can not be shared.\n"); - log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values)); - for (int i = SIZE(sat_model_values)-1; i >= 0; i--) + log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), GetSize(sat_model_values)); + for (int i = GetSize(sat_model_values)-1; i >= 0; i--) log("%c", sat_model_values[i] ? '1' : '0'); log("\n"); continue; @@ -1331,7 +1331,7 @@ struct ShareWorker } if (!cells_to_remove.empty()) { - log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module)); + log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), log_id(module)); for (auto c : cells_to_remove) { log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type)); module->remove(c); diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index 58a6d1b0..89b1f885 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -65,20 +65,20 @@ struct WreduceWorker SigSpec sig_y = mi.sigmap(cell->getPort("\\Y")); std::vector<SigBit> bits_removed; - for (int i = SIZE(sig_y)-1; i >= 0; i--) + for (int i = GetSize(sig_y)-1; i >= 0; i--) { auto info = mi.query(sig_y[i]); - if (!info->is_output && SIZE(info->ports) <= 1) { + if (!info->is_output && GetSize(info->ports) <= 1) { bits_removed.push_back(Sx); continue; } SigBit ref = sig_a[i]; - for (int k = 0; k < SIZE(sig_s); k++) { - if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i]) + for (int k = 0; k < GetSize(sig_s); k++) { + if (ref != Sx && sig_b[k*GetSize(sig_a) + i] != Sx && ref != sig_b[k*GetSize(sig_a) + i]) goto no_match_ab; - if (sig_b[k*SIZE(sig_a) + i] != Sx) - ref = sig_b[k*SIZE(sig_a) + i]; + if (sig_b[k*GetSize(sig_a) + i] != Sx) + ref = sig_b[k*GetSize(sig_a) + i]; } if (0) no_match_ab: @@ -90,10 +90,10 @@ struct WreduceWorker return; SigSpec sig_removed; - for (int i = SIZE(bits_removed)-1; i >= 0; i--) + for (int i = GetSize(bits_removed)-1; i >= 0; i--) sig_removed.append_bit(bits_removed[i]); - if (SIZE(bits_removed) == SIZE(sig_y)) { + if (GetSize(bits_removed) == GetSize(sig_y)) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->connect(sig_y, sig_removed); module->remove(cell); @@ -101,10 +101,10 @@ struct WreduceWorker } log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n", - SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type)); + GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type)); - int n_removed = SIZE(sig_removed); - int n_kept = SIZE(sig_y) - SIZE(sig_removed); + int n_removed = GetSize(sig_removed); + int n_kept = GetSize(sig_y) - GetSize(sig_removed); SigSpec new_work_queue_bits; new_work_queue_bits.append(sig_a.extract(n_kept, n_removed)); @@ -114,9 +114,9 @@ struct WreduceWorker SigSpec new_sig_y = sig_y.extract(0, n_kept); SigSpec new_sig_b; - for (int k = 0; k < SIZE(sig_s); k++) { - new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept)); - new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed)); + for (int k = 0; k < GetSize(sig_s); k++) { + new_sig_b.append(sig_b.extract(k*GetSize(sig_a), n_kept)); + new_work_queue_bits.append(sig_b.extract(k*GetSize(sig_a) + n_kept, n_removed)); } for (auto bit : new_work_queue_bits) @@ -139,24 +139,24 @@ struct WreduceWorker port_signed = false; int bits_removed = 0; - if (SIZE(sig) > max_port_size) { - bits_removed = SIZE(sig) - max_port_size; + if (GetSize(sig) > max_port_size) { + bits_removed = GetSize(sig) - max_port_size; for (auto bit : sig.extract(max_port_size, bits_removed)) work_queue_bits.insert(bit); sig = sig.extract(0, max_port_size); } if (port_signed) { - while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2]) - work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2]) + work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; } else { - while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0) - work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++; + while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == S0) + work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; } if (bits_removed) { log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); + bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort(stringf("\\%c", port), sig); did_something = true; } @@ -175,12 +175,12 @@ struct WreduceWorker // Reduce size of ports A and B based on constant input bits and size of output port - int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1; - int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1; + int max_port_a_size = cell->hasPort("\\A") ? GetSize(cell->getPort("\\A")) : -1; + int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1; if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) { - max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y"))); - max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y"))); + max_port_a_size = std::min(max_port_a_size, GetSize(cell->getPort("\\Y"))); + max_port_b_size = std::min(max_port_b_size, GetSize(cell->getPort("\\Y"))); } bool port_a_signed = false; @@ -201,14 +201,14 @@ struct WreduceWorker if (port_a_signed && cell->type == "$shr") { // do not reduce size of output on $shr cells with signed A inputs } else { - while (SIZE(sig) > 0) + while (GetSize(sig) > 0) { - auto info = mi.query(sig[SIZE(sig)-1]); + auto info = mi.query(sig[GetSize(sig)-1]); - if (info->is_output || SIZE(info->ports) > 1) + if (info->is_output || GetSize(info->ports) > 1) break; - sig.remove(SIZE(sig)-1); + sig.remove(GetSize(sig)-1); bits_removed++; } } @@ -218,8 +218,8 @@ struct WreduceWorker bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); int a_size = 0, b_size = 0; - if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A")); - if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B")); + if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A")); + if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B")); int max_y_size = std::max(a_size, b_size); @@ -229,14 +229,14 @@ struct WreduceWorker if (cell->type == "$mul") max_y_size = a_size + b_size; - while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) { - module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0); - sig.remove(SIZE(sig)-1); + while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) { + module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : S0); + sig.remove(GetSize(sig)-1); bits_removed++; } } - if (SIZE(sig) == 0) { + if (GetSize(sig) == 0) { log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type)); module->remove(cell); return; @@ -244,7 +244,7 @@ struct WreduceWorker if (bits_removed) { log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n", - bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); + bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); cell->setPort("\\Y", sig); did_something = true; } @@ -288,19 +288,19 @@ struct WreduceWorker if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0) continue; - for (int i = SIZE(w)-1; i >= 0; i--) { + for (int i = GetSize(w)-1; i >= 0; i--) { SigBit bit(w, i); auto info = mi.query(bit); - if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0)) + if (info && (info->is_input || info->is_output || GetSize(info->ports) > 0)) break; unused_top_bits++; } - if (0 < unused_top_bits && unused_top_bits < SIZE(w)) { - log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w)); + if (0 < unused_top_bits && unused_top_bits < GetSize(w)) { + log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); Wire *nw = module->addWire(NEW_ID, w); - nw->width = SIZE(w) - unused_top_bits; - module->connect(nw, SigSpec(w).extract(0, SIZE(nw))); + nw->width = GetSize(w) - unused_top_bits; + module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); module->swap_names(w, nw); } } |