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-rw-r--r--passes/opt/opt_clean.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 68fb2e72..23fc48d5 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -189,7 +189,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool
for (auto &it : module->wires) {
RTLIL::Wire *wire = it.second;
for (int i = 0; i < wire->width; i++) {
- RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, 1, i), s2 = assign_map(s1);
+ RTLIL::SigSpec s1 = RTLIL::SigSpec(wire, i), s2 = assign_map(s1);
if (!compare_signals(s1, s2, register_signals, connected_signals, direct_wires))
assign_map.add(s1);
}