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-rw-r--r--passes/sat/freduce.cc7
1 files changed, 4 insertions, 3 deletions
diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc
index 77263f6a..f2963163 100644
--- a/passes/sat/freduce.cc
+++ b/passes/sat/freduce.cc
@@ -687,7 +687,8 @@ struct FreduceWorker
}
std::map<RTLIL::SigBit, int> bitusage;
- module->rewrite_sigspecs(CountBitUsage(sigmap, bitusage));
+ CountBitUsage bitusage_worker(sigmap, bitusage);
+ module->rewrite_sigspecs(bitusage_worker);
if (!dump_prefix.empty())
dump();
@@ -759,7 +760,7 @@ struct FreduceWorker
struct FreducePass : public Pass {
FreducePass() : Pass("freduce", "perform functional reduction") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -790,7 +791,7 @@ struct FreducePass : public Pass {
log("circuit that is analyzed.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
reduce_counter = 0;
reduce_stop_at = 0;