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-rw-r--r--passes/sat/share.cc13
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index 0c88b4d3..7141cea2 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -252,6 +252,19 @@ struct ShareWorker
if (config.generic_uni_ops.count(c1->type))
{
+ if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int())
+ {
+ RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0;
+ while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) {
+ c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1);
+ c1->setPort("\\A", {extbit, c1->getPort("\\A")});
+ }
+ while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) {
+ c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1);
+ c2->setPort("\\A", {extbit, c2->getPort("\\A")});
+ }
+ }
+
if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;