diff options
Diffstat (limited to 'passes/sat')
| -rw-r--r-- | passes/sat/eval.cc | 2 | ||||
| -rw-r--r-- | passes/sat/expose.cc | 18 | ||||
| -rw-r--r-- | passes/sat/freduce.cc | 2 | ||||
| -rw-r--r-- | passes/sat/sat.cc | 2 | ||||
| -rw-r--r-- | passes/sat/share.cc | 4 |
5 files changed, 14 insertions, 14 deletions
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index d4ff2a86..45423326 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -147,7 +147,7 @@ struct VlogHammerReporter SatGen satgen(&ez, &sigmap); satgen.model_undef = model_undef; - for (auto &c : module->cells) + for (auto &c : module->cells_) if (!satgen.importCell(c.second)) log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index c30e6e0c..24b812bb 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -82,7 +82,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu SigMap sigmap(module); SigPool dffsignals; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type) && it.second->has("\\Q")) dffsignals.add(sigmap(it.second->get("\\Q"))); } @@ -98,7 +98,7 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL: std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info; SigMap sigmap(module); - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (!design->selected(module, it.second)) continue; @@ -371,7 +371,7 @@ struct ExposePass : public Pass { shared_wires.insert(it.first); if (flag_evert) - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second)) shared_cells.insert(it.first); @@ -409,16 +409,16 @@ struct ExposePass : public Pass { { RTLIL::Cell *cell; - if (module->cells.count(it) == 0) + if (module->cells_.count(it) == 0) goto delete_shared_cell; - cell = module->cells.at(it); + cell = module->cells_.at(it); if (!design->selected(module, cell)) goto delete_shared_cell; if (!consider_cell(design, dff_cells[module], cell)) goto delete_shared_cell; - if (!compare_cells(first_module->cells.at(it), cell)) + if (!compare_cells(first_module->cells_.at(it), cell)) goto delete_shared_cell; if (0) @@ -475,7 +475,7 @@ struct ExposePass : public Pass { if (flag_cut) { - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (!ct.cell_known(it.second->type)) continue; for (auto &conn : it.second->connections_) @@ -503,7 +503,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); for (auto &cell_name : info.cells) { - RTLIL::Cell *cell = module->cells.at(cell_name); + RTLIL::Cell *cell = module->cells_.at(cell_name); std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) @@ -571,7 +571,7 @@ struct ExposePass : public Pass { { std::vector<RTLIL::Cell*> delete_cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (flag_shared) { if (shared_cells.count(it.first) == 0) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5d23318c..f8d5cf6c 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -607,7 +607,7 @@ struct FreduceWorker batches.push_back(sigmap(it.second).to_sigbit_set()); bits_full_total += it.second->width; } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> inputs, outputs; for (auto &port : it.second->connections()) { diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 90c67116..3e1c7222 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -317,7 +317,7 @@ struct SatHelper } int import_cell_counter = 0; - for (auto &c : module->cells) + for (auto &c : module->cells_) if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 0ee5af18..facacf19 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -61,7 +61,7 @@ struct ShareWorker queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (!fwd_ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second]; queue_bits.insert(bits.begin(), bits.end()); @@ -101,7 +101,7 @@ struct ShareWorker void find_shareable_cells() { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; |