summaryrefslogtreecommitdiff
path: root/passes/techmap/alumacc.cc
diff options
context:
space:
mode:
Diffstat (limited to 'passes/techmap/alumacc.cc')
-rw-r--r--passes/techmap/alumacc.cc19
1 files changed, 13 insertions, 6 deletions
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 9f6dd02d..dc7d416b 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -55,19 +55,19 @@ struct AlumaccWorker
RTLIL::SigSpec get_gt() {
if (GetSize(cached_gt) == 0)
- cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
+ cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
return cached_gt;
}
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
- cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
+ cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->get_src_attribute());
return cached_eq;
}
RTLIL::SigSpec get_ne() {
if (GetSize(cached_ne) == 0)
- cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
+ cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
return cached_ne;
}
@@ -75,7 +75,7 @@ struct AlumaccWorker
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort("\\CO");
log_assert(GetSize(cached_cf) >= 1);
- cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1]);
+ cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
}
return cached_cf;
}
@@ -352,10 +352,13 @@ struct AlumaccWorker
{
auto n = it.second;
auto cell = module->addCell(NEW_ID, "$macc");
+
macc_counter++;
log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
+ cell->set_src_attribute(n->cell->get_src_attribute());
+
n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
cell->setPort("\\Y", n->y);
@@ -452,6 +455,7 @@ struct AlumaccWorker
void replace_alu()
{
+ std::string src("");
for (auto &it1 : sig_alu)
for (auto n : it1.second)
{
@@ -475,6 +479,9 @@ struct AlumaccWorker
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
+ if (n->cells.size() > 0)
+ n->alu_cell->set_src_attribute(n->cells[0]->get_src_attribute());
+
n->alu_cell->setPort("\\A", n->a);
n->alu_cell->setPort("\\B", n->b);
n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
@@ -532,7 +539,7 @@ struct AlumaccWorker
struct AlumaccPass : public Pass {
AlumaccPass() : Pass("alumacc", "extract ALU and MACC cells") { }
- virtual void help()
+ void help() YS_OVERRIDE
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
@@ -542,7 +549,7 @@ struct AlumaccPass : public Pass {
log("and $macc cells.\n");
log("\n");
}
- virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+ void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{
log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");