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-rw-r--r--passes/techmap/.gitignore2
-rw-r--r--passes/techmap/Makefile.inc6
-rw-r--r--passes/techmap/techmap.cc4
3 files changed, 6 insertions, 6 deletions
diff --git a/passes/techmap/.gitignore b/passes/techmap/.gitignore
index ca9d3942..e6dcc6bc 100644
--- a/passes/techmap/.gitignore
+++ b/passes/techmap/.gitignore
@@ -1 +1 @@
-stdcells.inc
+techmap.inc
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index e54c018a..b49259a8 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -10,16 +10,16 @@ OBJS += passes/techmap/hilomap.o
OBJS += passes/techmap/extract.o
endif
-GENFILES += passes/techmap/stdcells.inc
+GENFILES += passes/techmap/techmap.inc
-passes/techmap/stdcells.inc: techlibs/common/stdcells.v
+passes/techmap/techmap.inc: techlibs/common/techmap.v
$(P) echo "// autogenerated from $<" > $@.new
$(Q) echo "static char stdcells_code[] = {" >> $@.new
$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
$(Q) echo "0};" >> $@.new
$(Q) mv $@.new $@
-passes/techmap/techmap.o: passes/techmap/stdcells.inc
+passes/techmap/techmap.o: passes/techmap/techmap.inc
TARGETS += yosys-filterlib
GENFILES += passes/techmap/filterlib.o
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 50936af0..2aa59e61 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -26,7 +26,7 @@
#include <stdio.h>
#include <string.h>
-#include "passes/techmap/stdcells.inc"
+#include "passes/techmap/techmap.inc"
// see simplemap.cc
extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
@@ -790,7 +790,7 @@ struct TechmapPass : public Pass {
RTLIL::Design *map = new RTLIL::Design;
if (map_files.empty()) {
FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
- Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
+ Frontend::frontend_call(map, f, "<techmap.v>", verilog_frontend);
fclose(f);
} else
for (auto &fn : map_files)