4 files changed, 10 insertions, 10 deletions
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index eabc56bd..01284656 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -388,7 +388,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 	log("Mapping DFF cells in module `%s':\n", module->name.c_str());
 
 	std::vector<RTLIL::Cell*> cell_list;
-	for (auto &it : module->cells) {
+	for (auto &it : module->cells_) {
 		if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0)
 			cell_list.push_back(it.second);
 	}
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 813e0e3e..b66a11b8 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -182,7 +182,7 @@ namespace
 
 		std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count;
 		if (max_fanout > 0)
-			for (auto &cell_it : mod->cells)
+			for (auto &cell_it : mod->cells_)
 			{
 				RTLIL::Cell *cell = cell_it.second;
 				if (!sel || sel->selected(mod, cell))
@@ -196,7 +196,7 @@ namespace
 			}
 
 		// create graph nodes from cells
-		for (auto &cell_it : mod->cells)
+		for (auto &cell_it : mod->cells_)
 		{
 			RTLIL::Cell *cell = cell_it.second;
 			if (sel && !sel->selected(mod, cell))
@@ -253,7 +253,7 @@ namespace
 		}
 
 		// mark external signals (used in non-selected cells)
-		for (auto &cell_it : mod->cells)
+		for (auto &cell_it : mod->cells_)
 		{
 			RTLIL::Cell *cell = cell_it.second;
 			if (sel && !sel->selected(mod, cell))
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 355c07c8..8c7f6423 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -439,7 +439,7 @@ struct SimplemapPass : public Pass {
 			if (!design->selected(mod_it.second))
 				continue;
 			std::vector<RTLIL::Cell*> delete_cells;
-			for (auto &cell_it : mod_it.second->cells) {
+			for (auto &cell_it : mod_it.second->cells_) {
 				if (mappers.count(cell_it.second->type) == 0)
 					continue;
 				if (!design->selected(mod_it.second, cell_it.second))
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 03aac669..86d9e73a 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -116,7 +116,7 @@ struct TechmapWorker
 
 		std::string orig_cell_name;
 		if (!flatten_mode)
-			for (auto &it : tpl->cells)
+			for (auto &it : tpl->cells_)
 				if (it.first == "\\_TECHMAP_REPLACE_") {
 					orig_cell_name = cell->name;
 					module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
@@ -180,7 +180,7 @@ struct TechmapWorker
 			}
 		}
 
-		for (auto &it : tpl->cells)
+		for (auto &it : tpl->cells_)
 		{
 			RTLIL::IdString c_name = it.second->name;
 
@@ -224,15 +224,15 @@ struct TechmapWorker
 		std::vector<std::string> cell_names;
 
 		SigMap sigmap(module);
-		for (auto &cell_it : module->cells)
+		for (auto &cell_it : module->cells_)
 			cell_names.push_back(cell_it.first);
 
 		for (auto &cell_name : cell_names)
 		{
-			if (module->cells.count(cell_name) == 0)
+			if (module->cells_.count(cell_name) == 0)
 				continue;
 
-			RTLIL::Cell *cell = module->cells[cell_name];
+			RTLIL::Cell *cell = module->cells_[cell_name];
 
 			if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
 				continue;