24 files changed, 1615 insertions, 119 deletions

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 8112516c..b5024fa9 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -7,6 +7,9 @@ OBJS += passes/techmap/libparse.o
 
 ifeq ($(ENABLE_ABC),1)
 OBJS += passes/techmap/abc.o
+ifneq ($(ABCEXTERNAL),)
+passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
+endif
 endif
 
 ifneq ($(SMALL),1)
@@ -23,6 +26,11 @@ OBJS += passes/techmap/tribuf.o
 OBJS += passes/techmap/lut2mux.o
 OBJS += passes/techmap/nlutmap.o
 OBJS += passes/techmap/dffsr2dff.o
+OBJS += passes/techmap/shregmap.o
+OBJS += passes/techmap/deminout.o
+OBJS += passes/techmap/insbuf.o
+OBJS += passes/techmap/attrmvcp.o
+OBJS += passes/techmap/attrmap.o
 endif
 
 GENFILES += passes/techmap/techmap.inc
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 7da26602..cc79296c 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -29,15 +29,17 @@
 // Kahn, Arthur B. (1962), "Topological sorting of large networks", Communications of the ACM 5 (11): 558-562, doi:10.1145/368996.369025
 // http://en.wikipedia.org/wiki/Topological_sorting
 
-#define ABC_COMMAND_LIB "strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}"
-#define ABC_COMMAND_CTR "strash; scorr; ifraig; retime {D}; strash; dch -f; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
-#define ABC_COMMAND_LUT "strash; scorr; ifraig; retime; strash; dch -f; if"
-#define ABC_COMMAND_DFL "strash; scorr; ifraig; retime; strash; dch -f; map"
-
-#define ABC_FAST_COMMAND_LIB "retime {D}; map {D}"
-#define ABC_FAST_COMMAND_CTR "retime {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
-#define ABC_FAST_COMMAND_LUT "retime; if"
-#define ABC_FAST_COMMAND_DFL "retime; map"
+#define ABC_COMMAND_LIB "strash; dc2; scorr; ifraig; retime -o {D}; strash; dch -f; map {D}"
+#define ABC_COMMAND_CTR "strash; dc2; scorr; ifraig; retime -o {D}; strash; dch -f; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
+#define ABC_COMMAND_LUT "strash; dc2; scorr; ifraig; retime -o; strash; dch -f; if; mfs"
+#define ABC_COMMAND_SOP "strash; dc2; scorr; ifraig; retime -o; strash; dch -f; cover {I} {P}"
+#define ABC_COMMAND_DFL "strash; dc2; scorr; ifraig; retime -o; strash; dch -f; map"
+
+#define ABC_FAST_COMMAND_LIB "retime -o {D}; map {D}"
+#define ABC_FAST_COMMAND_CTR "retime -o {D}; map {D}; buffer; upsize {D}; dnsize {D}; stime -p"
+#define ABC_FAST_COMMAND_LUT "retime -o; if"
+#define ABC_FAST_COMMAND_SOP "retime -o; cover -I {I} -P {P}"
+#define ABC_FAST_COMMAND_DFL "retime -o; map"
 
 #include "kernel/register.h"
 #include "kernel/sigtools.h"
@@ -593,7 +595,8 @@ struct abc_output_filter
 
 void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
 		std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
-		bool keepff, std::string delay_target, bool fast_mode, const std::vector<RTLIL::Cell*> &cells, bool show_tempdir)
+		bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, bool fast_mode,
+		const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
 {
 	module = current_module;
 	map_autoidx = autoidx++;
@@ -616,7 +619,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 	if (!cleanup)
 		tempdir_name[0] = tempdir_name[4] = '_';
 	tempdir_name = make_temp_dir(tempdir_name);
-	log_header("Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
+	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
 			module->name.c_str(), replace_tempdir(tempdir_name, tempdir_name, show_tempdir).c_str());
 
 	std::string abc_script = stringf("read_blif %s/input.blif; ", tempdir_name.c_str());
@@ -642,16 +645,30 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 					abc_script += script_file[i];
 		} else
 			abc_script += stringf("source %s", script_file.c_str());
-	} else if (!lut_costs.empty())
+	} else if (!lut_costs.empty()) {
+		bool all_luts_cost_same = true;
+		for (int this_cost : lut_costs)
+			if (this_cost != lut_costs.front())
+				all_luts_cost_same = false;
 		abc_script += fast_mode ? ABC_FAST_COMMAND_LUT : ABC_COMMAND_LUT;
-	else if (!liberty_file.empty())
+		if (all_luts_cost_same && !fast_mode)
+			abc_script += "; lutpack";
+	} else if (!liberty_file.empty())
 		abc_script += constr_file.empty() ? (fast_mode ? ABC_FAST_COMMAND_LIB : ABC_COMMAND_LIB) : (fast_mode ? ABC_FAST_COMMAND_CTR : ABC_COMMAND_CTR);
+	else if (sop_mode)
+		abc_script += fast_mode ? ABC_FAST_COMMAND_SOP : ABC_COMMAND_SOP;
 	else
 		abc_script += fast_mode ? ABC_FAST_COMMAND_DFL : ABC_COMMAND_DFL;
 
 	for (size_t pos = abc_script.find("{D}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
 		abc_script = abc_script.substr(0, pos) + delay_target + abc_script.substr(pos+3);
 
+	for (size_t pos = abc_script.find("{I}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
+		abc_script = abc_script.substr(0, pos) + sop_inputs + abc_script.substr(pos+3);
+
+	for (size_t pos = abc_script.find("{P}"); pos != std::string::npos; pos = abc_script.find("{D}", pos))
+		abc_script = abc_script.substr(0, pos) + sop_products + abc_script.substr(pos+3);
+
 	abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
 	abc_script = add_echos_to_abc_cmd(abc_script);
 
@@ -828,7 +845,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 
 	if (count_output > 0)
 	{
-		log_header("Executing ABC.\n");
+		log_header(design, "Executing ABC.\n");
 
 		buffer = stringf("%s/stdcells.genlib", tempdir_name.c_str());
 		f = fopen(buffer.c_str(), "wt");
@@ -892,13 +909,13 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		if (ifs.fail())
 			log_error("Can't open ABC output file `%s'.\n", buffer.c_str());
 
-		bool builtin_lib = liberty_file.empty() && script_file.empty() && lut_costs.empty();
+		bool builtin_lib = liberty_file.empty();
 		RTLIL::Design *mapped_design = new RTLIL::Design;
-		parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_");
+		parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
 
 		ifs.close();
 
-		log_header("Re-integrating ABC results.\n");
+		log_header(design, "Re-integrating ABC results.\n");
 		RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"];
 		if (mapped_mod == NULL)
 			log_error("ABC output file does not contain a module `netlist'.\n");
@@ -910,10 +927,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 		}
 
 		std::map<std::string, int> cell_stats;
-		if (builtin_lib)
+		for (auto c : mapped_mod->cells())
 		{
-			for (auto &it : mapped_mod->cells_) {
-				RTLIL::Cell *c = it.second;
+			if (builtin_lib)
+			{
 				cell_stats[RTLIL::unescape_id(c->type)]++;
 				if (c->type == "\\ZERO" || c->type == "\\ONE") {
 					RTLIL::SigSig conn;
@@ -1052,60 +1069,57 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
 					design->select(module, cell);
 					continue;
 				}
-				log_abort();
 			}
-		}
-		else
-		{
-			for (auto &it : mapped_mod->cells_)
-			{
-				RTLIL::Cell *c = it.second;
-				cell_stats[RTLIL::unescape_id(c->type)]++;
-				if (c->type == "\\_const0_" || c->type == "\\_const1_") {
-					RTLIL::SigSig conn;
-					conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
-					conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
-					module->connect(conn);
-					continue;
-				}
-				if (c->type == "\\_dff_") {
-					log_assert(clk_sig.size() == 1);
-					RTLIL::Cell *cell;
-					if (en_sig.size() == 0) {
-						cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
-					} else {
-						log_assert(en_sig.size() == 1);
-						cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
-						cell->setPort("\\E", en_sig);
-					}
-					if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
-					cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
-					cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
-					cell->setPort("\\C", clk_sig);
-					design->select(module, cell);
-					continue;
-				}
-				if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
-					SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
-					SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
-					module->connect(my_y, my_a);
-					continue;
+
+			cell_stats[RTLIL::unescape_id(c->type)]++;
+
+			if (c->type == "\\_const0_" || c->type == "\\_const1_") {
+				RTLIL::SigSig conn;
+				conn.first = RTLIL::SigSpec(module->wires_[remap_name(c->connections().begin()->second.as_wire()->name)]);
+				conn.second = RTLIL::SigSpec(c->type == "\\_const0_" ? 0 : 1, 1);
+				module->connect(conn);
+				continue;
+			}
+
+			if (c->type == "\\_dff_") {
+				log_assert(clk_sig.size() == 1);
+				RTLIL::Cell *cell;
+				if (en_sig.size() == 0) {
+					cell = module->addCell(remap_name(c->name), clk_polarity ? "$_DFF_P_" : "$_DFF_N_");
+				} else {
+					log_assert(en_sig.size() == 1);
+					cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
+					cell->setPort("\\E", en_sig);
 				}
-				RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
 				if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
-				cell->parameters = c->parameters;
-				for (auto &conn : c->connections()) {
-					RTLIL::SigSpec newsig;
-					for (auto &c : conn.second.chunks()) {
-						if (c.width == 0)
-							continue;
-						log_assert(c.width == 1);
-						newsig.append(module->wires_[remap_name(c.wire->name)]);
-					}
-					cell->setPort(conn.first, newsig);
-				}
+				cell->setPort("\\D", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\D").as_wire()->name)]));
+				cell->setPort("\\Q", RTLIL::SigSpec(module->wires_[remap_name(c->getPort("\\Q").as_wire()->name)]));
+				cell->setPort("\\C", clk_sig);
 				design->select(module, cell);
+				continue;
+			}
+
+			if (c->type == "$lut" && GetSize(c->getPort("\\A")) == 1 && c->getParam("\\LUT").as_int() == 2) {
+				SigSpec my_a = module->wires_[remap_name(c->getPort("\\A").as_wire()->name)];
+				SigSpec my_y = module->wires_[remap_name(c->getPort("\\Y").as_wire()->name)];
+				module->connect(my_y, my_a);
+				continue;
+			}
+
+			RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
+			if (markgroups) cell->attributes["\\abcgroup"] = map_autoidx;
+			cell->parameters = c->parameters;
+			for (auto &conn : c->connections()) {
+				RTLIL::SigSpec newsig;
+				for (auto &c : conn.second.chunks()) {
+					if (c.width == 0)
+						continue;
+					log_assert(c.width == 1);
+					newsig.append(module->wires_[remap_name(c.wire->name)]);
+				}
+				cell->setPort(conn.first, newsig);
 			}
+			design->select(module, cell);
 		}
 
 		for (auto conn : mapped_mod->connections()) {
@@ -1167,7 +1181,11 @@ struct AbcPass : public Pass {
 		log("library to a target architecture.\n");
 		log("\n");
 		log("    -exe <command>\n");
-		log("        use the specified command name instead of \"yosys-abc\" to execute ABC.\n");
+#ifdef ABCEXTERNAL
+		log("        use the specified command instead of \"" ABCEXTERNAL "\" to execute ABC.\n");
+#else
+		log("        use the specified command instead of \"<yosys-bindir>/yosys-abc\" to execute ABC.\n");
+#endif
 		log("        This can e.g. be used to call a specific version of ABC or a wrapper.\n");
 		log("\n");
 		log("    -script <file>\n");
@@ -1186,9 +1204,15 @@ struct AbcPass : public Pass {
 		log("        for -liberty with -constr:\n");
 		log("%s\n", fold_abc_cmd(ABC_COMMAND_CTR).c_str());
 		log("\n");
-		log("        for -lut:\n");
+		log("        for -lut/-luts (only one LUT size):\n");
+		log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT "; lutpack").c_str());
+		log("\n");
+		log("        for -lut/-luts (different LUT sizes):\n");
 		log("%s\n", fold_abc_cmd(ABC_COMMAND_LUT).c_str());
 		log("\n");
+		log("        for -sop:\n");
+		log("%s\n", fold_abc_cmd(ABC_COMMAND_SOP).c_str());
+		log("\n");
 		log("        otherwise:\n");
 		log("%s\n", fold_abc_cmd(ABC_COMMAND_DFL).c_str());
 		log("\n");
@@ -1202,9 +1226,12 @@ struct AbcPass : public Pass {
 		log("        for -liberty with -constr:\n");
 		log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_CTR).c_str());
 		log("\n");
-		log("        for -lut:\n");
+		log("        for -lut/-luts:\n");
 		log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_LUT).c_str());
 		log("\n");
+		log("        for -sop:\n");
+		log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_SOP).c_str());
+		log("\n");
 		log("        otherwise:\n");
 		log("%s\n", fold_abc_cmd(ABC_FAST_COMMAND_DFL).c_str());
 		log("\n");
@@ -1227,6 +1254,14 @@ struct AbcPass : public Pass {
 		log("        set delay target. the string {D} in the default scripts above is\n");
 		log("        replaced by this option when used, and an empty string otherwise.\n");
 		log("\n");
+		log("    -I <num>\n");
+		log("        maximum number of SOP inputs.\n");
+		log("        (replaces {I} in the default scripts above)\n");
+		log("\n");
+		log("    -P <num>\n");
+		log("        maximum number of SOP products.\n");
+		log("        (replaces {P} in the default scripts above)\n");
+		log("\n");
 		log("    -lut <width>\n");
 		log("        generate netlist using luts of (max) the specified width.\n");
 		log("\n");
@@ -1240,6 +1275,9 @@ struct AbcPass : public Pass {
 		log("        generate netlist using luts. Use the specified costs for luts with 1,\n");
 		log("        2, 3, .. inputs.\n");
 		log("\n");
+		log("    -sop\n");
+		log("        map to sum-of-product cells and inverters\n");
+		log("\n");
 		// log("    -mux4, -mux8, -mux16\n");
 		// log("        try to extract 4-input, 8-input, and/or 16-input muxes\n");
 		// log("        (ignored when used with -liberty or -lut)\n");
@@ -1286,13 +1324,18 @@ struct AbcPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ABC pass (technology mapping using ABC).\n");
+		log_header(design, "Executing ABC pass (technology mapping using ABC).\n");
 		log_push();
 
+#ifdef ABCEXTERNAL
+		std::string exe_file = ABCEXTERNAL;
+#else
 		std::string exe_file = proc_self_dirname() + "yosys-abc";
-		std::string script_file, liberty_file, constr_file, clk_str, delay_target;
+#endif
+		std::string script_file, liberty_file, constr_file, clk_str;
+		std::string delay_target, sop_inputs, sop_products;
 		bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
-		bool show_tempdir = false;
+		bool show_tempdir = false, sop_mode = false;
 		vector<int> lut_costs;
 		markgroups = false;
 
@@ -1302,9 +1345,11 @@ struct AbcPass : public Pass {
 		enabled_gates.clear();
 
 #ifdef _WIN32
+#ifndef ABCEXTERNAL
 		if (!check_file_exists(exe_file + ".exe") && check_file_exists(proc_self_dirname() + "..\\yosys-abc.exe"))
 			exe_file = proc_self_dirname() + "..\\yosys-abc";
 #endif
+#endif
 
 		size_t argidx;
 		char pwd [PATH_MAX];
@@ -1340,6 +1385,14 @@ struct AbcPass : public Pass {
 				delay_target = "-D " + args[++argidx];
 				continue;
 			}
+			if (arg == "-I" && argidx+1 < args.size()) {
+				sop_inputs = "-I " + args[++argidx];
+				continue;
+			}
+			if (arg == "-P" && argidx+1 < args.size()) {
+				sop_products = "-P " + args[++argidx];
+				continue;
+			}
 			if (arg == "-lut" && argidx+1 < args.size()) {
 				string arg = args[++argidx];
 				size_t pos = arg.find_first_of(':');
@@ -1374,6 +1427,10 @@ struct AbcPass : public Pass {
 				}
 				continue;
 			}
+			if (arg == "-sop") {
+				sop_mode = true;
+				continue;
+			}
 			if (arg == "-mux4") {
 				map_mux4 = true;
 				continue;
@@ -1447,7 +1504,8 @@ struct AbcPass : public Pass {
 			if (mod->processes.size() > 0)
 				log("Skipping module %s as it contains processes.\n", log_id(mod));
 			else if (!dff_mode || !clk_str.empty())
-				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff, delay_target, fast_mode, mod->selected_cells(), show_tempdir);
+				abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
+						delay_target, sop_inputs, sop_products, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
 			else
 			{
 				assign_map.set(mod);
@@ -1580,7 +1638,7 @@ struct AbcPass : public Pass {
 					assigned_cells_reverse[cell] = key;
 				}
 
-				log_header("Summary of detected clock domains:\n");
+				log_header(design, "Summary of detected clock domains:\n");
 				for (auto &it : assigned_cells)
 					log("  %d cells in clk=%s%s, en=%s%s\n", GetSize(it.second),
 							std::get<0>(it.first) ? "" : "!", log_signal(std::get<1>(it.first)),
@@ -1591,8 +1649,8 @@ struct AbcPass : public Pass {
 					clk_sig = assign_map(std::get<1>(it.first));
 					en_polarity = std::get<2>(it.first);
 					en_sig = assign_map(std::get<3>(it.first));
-					abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs,
-							!clk_sig.empty(), "$", keepff, delay_target, fast_mode, it.second, show_tempdir);
+					abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
+							keepff, delay_target, sop_inputs, sop_products, fast_mode, it.second, show_tempdir, sop_mode);
 					assign_map.set(mod);
 				}
 			}
diff --git a/passes/techmap/aigmap.cc b/passes/techmap/aigmap.cc
index db1c731e..b9ac7ade 100644
--- a/passes/techmap/aigmap.cc
+++ b/passes/techmap/aigmap.cc
@@ -41,7 +41,7 @@ struct AigmapPass : public Pass {
 	{
 		bool nand_mode = false;
 
-		log_header("Executing AIGMAP pass (map logic to AIG).\n");
+		log_header(design, "Executing AIGMAP pass (map logic to AIG).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 3c7ff4b9..9f6dd02d 100644
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -544,7 +544,7 @@ struct AlumaccPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing ALUMACC pass (create $alu and $macc cells).\n");
+		log_header(design, "Executing ALUMACC pass (create $alu and $macc cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/techmap/attrmap.cc b/passes/techmap/attrmap.cc
new file mode 100644
index 00000000..f715b63e
--- /dev/null
+++ b/passes/techmap/attrmap.cc
@@ -0,0 +1,250 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+Const make_value(string &value)
+{
+	if (GetSize(value) >= 2 && value.front() == '"' && value.back() == '"')
+		return Const(value.substr(1, GetSize(value)-2));
+
+	SigSpec sig;
+	SigSpec::parse(sig, nullptr, value);
+	return sig.as_const();
+}
+
+bool match_name(string &name, IdString &id, bool ignore_case=false)
+{
+	string str1 = RTLIL::escape_id(name);
+	string str2 = id.str();
+
+	if (ignore_case)
+		return !strcasecmp(str1.c_str(), str2.c_str());
+
+	return str1 == str2;
+}
+
+bool match_value(string &value, Const &val, bool ignore_case=false)
+{
+	if (ignore_case && ((val.flags & RTLIL::CONST_FLAG_STRING) != 0) && GetSize(value) && value.front() == '"' && value.back() == '"') {
+		string str1 = value.substr(1, GetSize(value)-2);
+		string str2 = val.decode_string();
+		return !strcasecmp(str1.c_str(), str2.c_str());
+	}
+
+	return make_value(value) == val;
+}
+
+struct AttrmapAction {
+	virtual ~AttrmapAction() { }
+	virtual bool apply(IdString &id, Const &val) = 0;
+};
+
+struct AttrmapTocase : AttrmapAction {
+	string name;
+	virtual bool apply(IdString &id, Const&) {
+		if (match_name(name, id, true))
+			id = RTLIL::escape_id(name);
+		return true;
+	}
+};
+
+struct AttrmapRename : AttrmapAction {
+	string old_name, new_name;
+	virtual bool apply(IdString &id, Const&) {
+		if (match_name(old_name, id))
+			id = RTLIL::escape_id(new_name);
+		return true;
+	}
+};
+
+struct AttrmapMap : AttrmapAction {
+	bool imap;
+	string old_name, new_name;
+	string old_value, new_value;
+	virtual bool apply(IdString &id, Const &val) {
+		if (match_name(old_name, id) && match_value(old_value, val, true)) {
+			id = RTLIL::escape_id(new_name);
+			val = make_value(new_value);
+		}
+		return true;
+	}
+};
+
+struct AttrmapRemove : AttrmapAction {
+	string name, value;
+	virtual bool apply(IdString &id, Const &val) {
+		return !(match_name(name, id) && match_value(value, val));
+	}
+};
+
+void attrmap_apply(string objname, vector<std::unique_ptr<AttrmapAction>> &actions, dict<RTLIL::IdString, RTLIL::Const> &attributes)
+{
+	dict<RTLIL::IdString, RTLIL::Const> new_attributes;
+
+	for (auto attr : attributes)
+	{
+		auto new_attr = attr;
+		for (auto &action : actions)
+			if (!action->apply(new_attr.first, new_attr.second))
+				goto delete_this_attr;
+
+		if (new_attr != attr)
+			log("Changed attribute on %s: %s=%s -> %s=%s\n", objname.c_str(),
+					log_id(attr.first), log_const(attr.second), log_id(new_attr.first), log_const(new_attr.second));
+
+		new_attributes[new_attr.first] = new_attr.second;
+
+		if (0)
+	delete_this_attr:
+			log("Removed attribute on %s: %s=%s\n", objname.c_str(), log_id(attr.first), log_const(attr.second));
+	}
+
+	attributes.swap(new_attributes);
+}
+
+struct AttrmapPass : public Pass {
+	AttrmapPass() : Pass("attrmap", "renaming attributes") { }
+	virtual void help()
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    attrmap [options] [selection]\n");
+		log("\n");
+		log("This command renames attributes and/or mapps key/value pairs to\n");
+		log("other key/value pairs.\n");
+		log("\n");
+		log("    -tocase <name>\n");
+		log("        Match attribute names case-insensitively and set it to the specified\n");
+		log("        name.\n");
+		log("\n");
+		log("    -rename <old_name> <new_name>\n");
+		log("        Rename attributes as specified\n");
+		log("\n");
+		log("    -map <old_name>=<old_value> <new_name>=<new_value>\n");
+		log("        Map key/value pairs as indicated.\n");
+		log("\n");
+		log("    -imap <old_name>=<old_value> <new_name>=<new_value>\n");
+		log("        Like -map, but use case-insensitive match for <old_value> when\n");
+		log("        it is a string value.\n");
+		log("\n");
+		log("    -remove <name>=<value>\n");
+		log("        Remove attributes matching this pattern.\n");
+		log("\n");
+		log("    -modattr\n");
+		log("        Operate on module attributes instead of attributes on wires and cells.\n");
+		log("\n");
+		log("For example, mapping Xilinx-style \"keep\" attributes to Yosys-style:\n");
+		log("\n");
+		log("    attrmap -tocase keep -imap keep=\"true\" keep=1 \\\n");
+		log("            -imap keep=\"false\" keep=0 -remove keep=0\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing ATTRMAP pass (move or copy attributes).\n");
+
+		bool modattr_mode = false;
+		vector<std::unique_ptr<AttrmapAction>> actions;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			std::string arg = args[argidx];
+			if (arg == "-tocase" && argidx+1 < args.size()) {
+				auto action = new AttrmapTocase;
+				action->name = args[++argidx];
+				actions.push_back(std::unique_ptr<AttrmapAction>(action));
+				continue;
+			}
+			if (arg == "-rename" && argidx+2 < args.size()) {
+				auto action = new AttrmapRename;
+				action->old_name = args[++argidx];
+				action->new_name = args[++argidx];
+				actions.push_back(std::unique_ptr<AttrmapAction>(action));
+				continue;
+			}
+			if ((arg == "-map" || arg == "-imap") && argidx+2 < args.size()) {
+				string arg1 = args[++argidx];
+				string arg2 = args[++argidx];
+				string val1, val2;
+				size_t p = arg1.find("=");
+				if (p != string::npos) {
+					val1 = arg1.substr(p+1);
+					arg1 = arg1.substr(0, p);
+				}
+				p = arg2.find("=");
+				if (p != string::npos) {
+					val2 = arg2.substr(p+1);
+					arg2 = arg2.substr(0, p);
+				}
+				auto action = new AttrmapMap;
+				action->imap = (arg == "-map");
+				action->old_name = arg1;
+				action->new_name = arg2;
+				action->old_value = val1;
+				action->new_value = val2;
+				actions.push_back(std::unique_ptr<AttrmapAction>(action));
+				continue;
+			}
+			if (arg == "-remove" && argidx+1 < args.size()) {
+				string arg1 = args[++argidx], val1;
+				size_t p = arg1.find("=");
+				if (p != string::npos) {
+					val1 = arg1.substr(p+1);
+					arg1 = arg1.substr(0, p);
+				}
+				auto action = new AttrmapRemove;
+				action->name = arg1;
+				action->value = val1;
+				actions.push_back(std::unique_ptr<AttrmapAction>(action));
+				continue;
+			}
+			if (arg == "-modattr") {
+				modattr_mode = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (modattr_mode)
+		{
+			for (auto module : design->selected_whole_modules())
+				attrmap_apply(stringf("%s", log_id(module)), actions, module->attributes);
+		}
+		else
+		{
+			for (auto module : design->selected_modules())
+			{
+				for (auto wire : module->selected_wires())
+					attrmap_apply(stringf("%s.%s", log_id(module), log_id(wire)), actions, wire->attributes);
+
+				for (auto cell : module->selected_cells())
+					attrmap_apply(stringf("%s.%s", log_id(module), log_id(cell)), actions, cell->attributes);
+			}
+		}
+	}
+} AttrmapPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/attrmvcp.cc b/passes/techmap/attrmvcp.cc
new file mode 100644
index 00000000..50eaf61d
--- /dev/null
+++ b/passes/techmap/attrmvcp.cc
@@ -0,0 +1,139 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct AttrmvcpPass : public Pass {
+	AttrmvcpPass() : Pass("attrmvcp", "move or copy attributes from wires to driving cells") { }
+	virtual void help()
+	{
+		log("\n");
+		log("    attrmvcp [options] [selection]\n");
+		log("\n");
+		log("Move or copy attributes on wires to the cells driving them.\n");
+		log("\n");
+		log("    -copy\n");
+		log("        By default, attributes are moved. This will only add\n");
+		log("        the attribute to the cell, without removing it from\n");
+		log("        the wire.\n");
+		log("\n");
+		log("    -purge\n");
+		log("        If no selected cell consumes the attribute, then it is\n");
+		log("        left on the wire by default. This option will cause the\n");
+		log("        attribute to be removed from the wire, even if no selected\n");
+		log("        cell takes it.\n");
+		log("\n");
+		log("    -driven\n");
+		log("        By default, attriburtes are moved to the cell driving the\n");
+		log("        wire. With this option set it will be moved to the cell\n");
+		log("        driven by the wire instead.\n");
+		log("\n");
+		log("    -attr <attrname>\n");
+		log("        Move or copy this attribute. This option can be used\n");
+		log("        multiple times.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing ATTRMVCP pass (move or copy attributes).\n");
+
+		bool copy_mode = false;
+		bool driven_mode = false;
+		bool purge_mode = false;
+		pool<IdString> attrnames;
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			std::string arg = args[argidx];
+			if (arg == "-copy") {
+				copy_mode = true;
+				continue;
+			}
+			if (arg == "-driven") {
+				driven_mode = true;
+				continue;
+			}
+			if (arg == "-purge") {
+				purge_mode = true;
+				continue;
+			}
+			if (arg == "-attr" && argidx+1 < args.size()) {
+				attrnames.insert(RTLIL::escape_id(args[++argidx]));
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			dict<SigBit, pool<Cell*>> net2cells;
+			SigMap sigmap(module);
+
+			for (auto cell : module->selected_cells())
+			for (auto &conn : cell->connections())
+				if (driven_mode) {
+					if (cell->input(conn.first))
+						for (auto bit : sigmap(conn.second))
+							net2cells[bit].insert(cell);
+				} else {
+					if (cell->output(conn.first))
+						for (auto bit : sigmap(conn.second))
+							net2cells[bit].insert(cell);
+				}
+
+			for (auto wire : module->selected_wires())
+			{
+				dict<IdString, Const> new_attributes;
+
+				for (auto attr : wire->attributes)
+				{
+					bool did_something = false;
+
+					if (!attrnames.count(attr.first)) {
+						new_attributes[attr.first] = attr.second;
+						continue;
+					}
+
+					for (auto bit : sigmap(wire))
+						if (net2cells.count(bit))
+							for (auto cell : net2cells.at(bit)) {
+								log("Moving attribute %s=%s from %s.%s to %s.%s.\n", log_id(attr.first), log_const(attr.second),
+										log_id(module), log_id(wire), log_id(module), log_id(cell));
+								cell->attributes[attr.first] = attr.second;
+								did_something = true;
+							}
+
+					if (!purge_mode && !did_something)
+						new_attributes[attr.first] = attr.second;
+				}
+
+				if (!copy_mode)
+					wire->attributes.swap(new_attributes);
+			}
+		}
+	}
+} AttrmvcpPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/deminout.cc b/passes/techmap/deminout.cc
new file mode 100644
index 00000000..ed4e4576
--- /dev/null
+++ b/passes/techmap/deminout.cc
@@ -0,0 +1,116 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct DeminoutPass : public Pass {
+	DeminoutPass() : Pass("deminout", "demote inout ports to input or output") { }
+	virtual void help()
+	{
+		log("\n");
+		log("    deminout [options] [selection]\n");
+		log("\n");
+		log("\"Demote\" inout ports to input or output ports, if possible.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing DEMINOUT pass (demote inout ports to input or output).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			// if (args[argidx] == "-bits") {
+			// 	flag_bits = true;
+			// 	continue;
+			// }
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		bool keep_running = true;
+
+		while (keep_running)
+		{
+			keep_running = false;
+
+			for (auto module : design->selected_modules())
+			{
+				SigMap sigmap(module);
+				pool<SigBit> bits_written, bits_used, bits_inout;
+				dict<SigBit, int> bits_numports;
+
+				for (auto wire : module->wires())
+					if (wire->port_id)
+						for (auto bit : sigmap(wire))
+							bits_numports[bit]++;
+
+				for (auto cell : module->cells())
+				for (auto &conn : cell->connections())
+				{
+					bool cellport_out = cell->output(conn.first) || !cell->known();
+					bool cellport_in = cell->input(conn.first) || !cell->known();
+
+					if (cellport_out && cellport_in)
+						for (auto bit : sigmap(conn.second))
+							bits_inout.insert(bit);
+
+					if (cellport_out)
+						for (auto bit : sigmap(conn.second))
+							bits_written.insert(bit);
+
+					if (cellport_in)
+						for (auto bit : sigmap(conn.second))
+							bits_used.insert(bit);
+				}
+
+				for (auto wire : module->selected_wires())
+					if (wire->port_input && wire->port_output)
+					{
+						bool new_input = false;
+						bool new_output = false;
+
+						for (auto bit : sigmap(wire))
+						{
+							if (bits_numports[bit] > 1 || bits_inout.count(bit))
+								new_input = true, new_output = true;
+
+							if (bits_written.count(bit))
+								new_output = true;
+							else if (bits_used.count(bit))
+								new_input = true;
+						}
+
+						if (new_input != new_output) {
+							log("Demoting inout port %s.%s to %s.\n", log_id(module), log_id(wire), new_input ? "input" : "output");
+							wire->port_input = new_input;
+							wire->port_output = new_output;
+							keep_running = true;
+						}
+					}
+			}
+		}
+	}
+} DeminoutPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/dff2dffe.cc b/passes/techmap/dff2dffe.cc
index 51bfaade..1b8920bb 100644
--- a/passes/techmap/dff2dffe.cc
+++ b/passes/techmap/dff2dffe.cc
@@ -285,7 +285,7 @@ struct Dff2dffePass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
+		log_header(design, "Executing DFF2DFFE pass (transform $dff to $dffe where applicable).\n");
 
 		bool unmap_mode = false;
 		dict<IdString, IdString> direct_dict;
diff --git a/passes/techmap/dffinit.cc b/passes/techmap/dffinit.cc
index e0273f43..d737b342 100644
--- a/passes/techmap/dffinit.cc
+++ b/passes/techmap/dffinit.cc
@@ -41,7 +41,7 @@ struct DffinitPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFFINIT pass (set INIT param on FF cells).\n");
+		log_header(design, "Executing DFFINIT pass (set INIT param on FF cells).\n");
 
 		dict<IdString, dict<IdString, IdString>> ff_types;
 
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 4d7a1a70..c8104fb7 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -108,6 +108,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
 	LibertyAst *best_cell = NULL;
 	std::map<std::string, char> best_cell_ports;
 	int best_cell_pins = 0;
+	bool best_cell_noninv = false;
 	double best_cell_area = 0;
 
 	if (ast->id != "library")
@@ -155,6 +156,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
 
 		int num_pins = 0;
 		bool found_output = false;
+		bool found_noninv_output = false;
 		for (auto pin : cell->children)
 		{
 			if (pin->id != "pin" || pin->args.size() != 1)
@@ -175,10 +177,14 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
 					value.erase(pos, 1);
 				if (value == ff->args[0]) {
 					this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
+					if (cell_next_pol)
+						found_noninv_output = true;
 					found_output = true;
 				} else
 				if (value == ff->args[1]) {
 					this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
+					if (!cell_next_pol)
+						found_noninv_output = true;
 					found_output = true;
 				}
 			}
@@ -187,7 +193,7 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
 				this_cell_ports[pin->args[0]] = 0;
 		}
 
-		if (!found_output || (best_cell != NULL && num_pins > best_cell_pins))
+		if (!found_output || (best_cell != NULL && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
 			continue;
 
 		if (best_cell != NULL && num_pins == best_cell_pins && area > best_cell_area)
@@ -196,12 +202,14 @@ static void find_cell(LibertyAst *ast, std::string cell_type, bool clkpol, bool
 		best_cell = cell;
 		best_cell_pins = num_pins;
 		best_cell_area = area;
+		best_cell_noninv = found_noninv_output;
 		best_cell_ports.swap(this_cell_ports);
 	continue_cell_loop:;
 	}
 
 	if (best_cell != NULL) {
-		log("  cell %s (pins=%d, area=%.2f) is a direct match for cell type %s.\n", best_cell->args[0].c_str(), best_cell_pins, best_cell_area, cell_type.c_str());
+		log("  cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
+				best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
 		if (prepare_mode) {
 			cell_mappings[cell_type].cell_name = cell_type;
 			cell_mappings[cell_type].ports["C"] = 'C';
@@ -221,6 +229,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
 	LibertyAst *best_cell = NULL;
 	std::map<std::string, char> best_cell_ports;
 	int best_cell_pins = 0;
+	bool best_cell_noninv = false;
 	double best_cell_area = 0;
 
 	if (ast->id != "library")
@@ -260,6 +269,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
 
 		int num_pins = 0;
 		bool found_output = false;
+		bool found_noninv_output = false;
 		for (auto pin : cell->children)
 		{
 			if (pin->id != "pin" || pin->args.size() != 1)
@@ -280,10 +290,14 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
 					value.erase(pos, 1);
 				if (value == ff->args[0]) {
 					this_cell_ports[pin->args[0]] = cell_next_pol ? 'Q' : 'q';
+					if (cell_next_pol)
+						found_noninv_output = true;
 					found_output = true;
 				} else
 				if (value == ff->args[1]) {
 					this_cell_ports[pin->args[0]] = cell_next_pol ? 'q' : 'Q';
+					if (!cell_next_pol)
+						found_noninv_output = true;
 					found_output = true;
 				}
 			}
@@ -292,7 +306,7 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
 				this_cell_ports[pin->args[0]] = 0;
 		}
 
-		if (!found_output || (best_cell != NULL && num_pins > best_cell_pins))
+		if (!found_output || (best_cell != NULL && (num_pins > best_cell_pins || (best_cell_noninv && !found_noninv_output))))
 			continue;
 
 		if (best_cell != NULL && num_pins == best_cell_pins && area > best_cell_area)
@@ -301,12 +315,14 @@ static void find_cell_sr(LibertyAst *ast, std::string cell_type, bool clkpol, bo
 		best_cell = cell;
 		best_cell_pins = num_pins;
 		best_cell_area = area;
+		best_cell_noninv = found_noninv_output;
 		best_cell_ports.swap(this_cell_ports);
 	continue_cell_loop:;
 	}
 
 	if (best_cell != NULL) {
-		log("  cell %s (pins=%d, area=%.2f) is a direct match for cell type %s.\n", best_cell->args[0].c_str(), best_cell_pins, best_cell_area, cell_type.c_str());
+		log("  cell %s (%sinv, pins=%d, area=%.2f) is a direct match for cell type %s.\n",
+				best_cell->args[0].c_str(), best_cell_noninv ? "non" : "", best_cell_pins, best_cell_area, cell_type.c_str());
 		if (prepare_mode) {
 			cell_mappings[cell_type].cell_name = cell_type;
 			cell_mappings[cell_type].ports["C"] = 'C';
@@ -531,7 +547,7 @@ struct DfflibmapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
+		log_header(design, "Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).\n");
 
 		std::string liberty_file;
 		bool prepare_mode = false;
diff --git a/passes/techmap/dffsr2dff.cc b/passes/techmap/dffsr2dff.cc
index 8dcbb4ed..0d4d5362 100644
--- a/passes/techmap/dffsr2dff.cc
+++ b/passes/techmap/dffsr2dff.cc
@@ -188,7 +188,7 @@ struct Dffsr2dffPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
+		log_header(design, "Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index fc73177c..71e29c60 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -442,7 +442,7 @@ struct ExtractPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing EXTRACT pass (map subcircuits to cells).\n");
+		log_header(design, "Executing EXTRACT pass (map subcircuits to cells).\n");
 		log_push();
 
 		SubCircuitSolver solver;
@@ -627,7 +627,7 @@ struct ExtractPass : public Pass {
 		std::map<std::string, RTLIL::Module*> needle_map, haystack_map;
 		std::vector<RTLIL::Module*> needle_list;
 
-		log_header("Creating graphs for SubCircuit library.\n");
+		log_header(design, "Creating graphs for SubCircuit library.\n");
 
 		if (!mine_mode)
 			for (auto &mod_it : map->modules_) {
@@ -654,7 +654,7 @@ struct ExtractPass : public Pass {
 		if (!mine_mode)
 		{
 			std::vector<SubCircuit::Solver::Result> results;
-			log_header("Running solver from SubCircuit library.\n");
+			log_header(design, "Running solver from SubCircuit library.\n");
 
 			std::sort(needle_list.begin(), needle_list.end(), compareSortNeedleList);
 
@@ -667,7 +667,7 @@ struct ExtractPass : public Pass {
 
 			if (results.size() > 0)
 			{
-				log_header("Substitute SubCircuits with cells.\n");
+				log_header(design, "Substitute SubCircuits with cells.\n");
 
 				for (int i = 0; i < int(results.size()); i++) {
 					auto &result = results[i];
@@ -688,7 +688,7 @@ struct ExtractPass : public Pass {
 		{
 			std::vector<SubCircuit::Solver::MineResult> results;
 
-			log_header("Running miner from SubCircuit library.\n");
+			log_header(design, "Running miner from SubCircuit library.\n");
 			solver.mine(results, mine_cells_min, mine_cells_max, mine_min_freq, mine_limit_mod);
 
 			map = new RTLIL::Design;
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index a0bd2f9a..82cecac2 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -76,7 +76,7 @@ struct HilomapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing HILOMAP pass (mapping to constant drivers).\n");
+		log_header(design, "Executing HILOMAP pass (mapping to constant drivers).\n");
 
 		hicell_celltype = std::string();
 		hicell_portname = std::string();
diff --git a/passes/techmap/insbuf.cc b/passes/techmap/insbuf.cc
new file mode 100644
index 00000000..aa81468d
--- /dev/null
+++ b/passes/techmap/insbuf.cc
@@ -0,0 +1,94 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct InsbufPass : public Pass {
+	InsbufPass() : Pass("insbuf", "insert buffer cells for connected wires") { }
+	virtual void help()
+	{
+		log("\n");
+		log("    insbuf [options] [selection]\n");
+		log("\n");
+		log("Insert buffer cells into the design for directly connected wires.\n");
+		log("\n");
+		log("    -buf <celltype> <in-portname> <out-portname>\n");
+		log("        Use the given cell type instead of $_BUF_. (Notice that the next\n");
+		log("        call to \"clean\" will remove all $_BUF_ in the design.)\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
+
+		std::string celltype = "$_BUF_", in_portname = "\\A", out_portname = "\\Y";
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			std::string arg = args[argidx];
+			if (arg == "-buf" && argidx+3 < args.size()) {
+				celltype = args[++argidx];
+				in_portname = args[++argidx];
+				out_portname = args[++argidx];
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_modules())
+		{
+			std::vector<RTLIL::SigSig> new_connections;
+
+			for (auto &conn : module->connections())
+			{
+				RTLIL::SigSig new_conn;
+
+				for (int i = 0; i < GetSize(conn.first); i++)
+				{
+					SigBit lhs = conn.first[i];
+					SigBit rhs = conn.second[i];
+
+					if (lhs.wire && !design->selected(module, lhs.wire)) {
+						new_conn.first.append(lhs);
+						new_conn.second.append(rhs);
+						continue;
+					}
+
+					Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
+					cell->setPort(RTLIL::escape_id(in_portname), rhs);
+					cell->setPort(RTLIL::escape_id(out_portname), lhs);
+					log("Added %s.%s: %s -> %s\n", log_id(module), log_id(cell), log_signal(rhs), log_signal(lhs));
+				}
+
+				if (GetSize(new_conn.first))
+					new_connections.push_back(new_conn);
+			}
+
+			module->new_connections(new_connections);
+		}
+	}
+} InsbufPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 9dab40ca..4acbf7c0 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -17,9 +17,8 @@
  *
  */
 
-#include "kernel/register.h"
-#include "kernel/rtlil.h"
-#include "kernel/log.h"
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -48,12 +47,23 @@ struct IopadmapPass : public Pass {
 		log("        Map module input ports to the given cell type with the\n");
 		log("        given output port name. if a 2nd portname is given, the\n");
 		log("        signal is passed through the pad call, using the 2nd\n");
-		log("        portname as input.\n");
+		log("        portname as the port facing the module port.\n");
 		log("\n");
 		log("    -outpad <celltype> <portname>[:<portname>]\n");
 		log("    -inoutpad <celltype> <portname>[:<portname>]\n");
 		log("        Similar to -inpad, but for output and inout ports.\n");
 		log("\n");
+		log("    -toutpad <celltype> <portname>:<portname>[:<portname>]\n");
+		log("        Merges $_TBUF_ cells into the output pad cell. This takes precedence\n");
+		log("        over the other -outpad cell. The first portname is the enable input\n");
+		log("        of the tristate driver.\n");
+		log("\n");
+		log("    -tinoutpad <celltype> <portname>:<portname>:<portname>[:<portname>]\n");
+		log("        Merges $_TBUF_ cells into the inout pad cell. This takes precedence\n");
+		log("        over the other -inoutpad cell. The first portname is the enable input\n");
+		log("        of the tristate driver and the 2nd portname is the internal output\n");
+		log("        buffering the external signal.\n");
+		log("\n");
 		log("    -widthparam <param_name>\n");
 		log("        Use the specified parameter name to set the port width.\n");
 		log("\n");
@@ -65,14 +75,18 @@ struct IopadmapPass : public Pass {
 		log("        are wider. (the default behavior is to create word-wide\n");
 		log("        buffers using -widthparam to set the word size on the cell.)\n");
 		log("\n");
+		log("Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
+		log_header(design, "Executing IOPADMAP pass (mapping inputs/outputs to IO-PAD cells).\n");
 
 		std::string inpad_celltype, inpad_portname, inpad_portname2;
 		std::string outpad_celltype, outpad_portname, outpad_portname2;
 		std::string inoutpad_celltype, inoutpad_portname, inoutpad_portname2;
+		std::string toutpad_celltype, toutpad_portname, toutpad_portname2, toutpad_portname3;
+		std::string tinoutpad_celltype, tinoutpad_portname, tinoutpad_portname2, tinoutpad_portname3, tinoutpad_portname4;
 		std::string widthparam, nameparam;
 		bool flag_bits = false;
 
@@ -98,6 +112,21 @@ struct IopadmapPass : public Pass {
 				split_portname_pair(inoutpad_portname, inoutpad_portname2);
 				continue;
 			}
+			if (arg == "-toutpad" && argidx+2 < args.size()) {
+				toutpad_celltype = args[++argidx];
+				toutpad_portname = args[++argidx];
+				split_portname_pair(toutpad_portname, toutpad_portname2);
+				split_portname_pair(toutpad_portname2, toutpad_portname3);
+				continue;
+			}
+			if (arg == "-tinoutpad" && argidx+2 < args.size()) {
+				tinoutpad_celltype = args[++argidx];
+				tinoutpad_portname = args[++argidx];
+				split_portname_pair(tinoutpad_portname, tinoutpad_portname2);
+				split_portname_pair(tinoutpad_portname2, tinoutpad_portname3);
+				split_portname_pair(tinoutpad_portname3, tinoutpad_portname4);
+				continue;
+			}
 			if (arg == "-widthparam" && argidx+1 < args.size()) {
 				widthparam = args[++argidx];
 				continue;
@@ -116,12 +145,132 @@ struct IopadmapPass : public Pass {
 
 		for (auto module : design->selected_modules())
 		{
+			dict<IdString, pool<int>> skip_wires;
+
+			if (!toutpad_celltype.empty() || !tinoutpad_celltype.empty())
+			{
+				SigMap sigmap(module);
+				dict<SigBit, pair<IdString, pool<IdString>>> tbuf_bits;
+
+				for (auto cell : module->cells())
+					if (cell->type == "$_TBUF_") {
+						SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
+						tbuf_bits[bit].first = cell->name;
+					}
+
+				for (auto cell : module->cells())
+				for (auto port : cell->connections())
+				for (auto bit : sigmap(port.second))
+					if (tbuf_bits.count(bit))
+						tbuf_bits.at(bit).second.insert(cell->name);
+
+				for (auto wire : module->selected_wires())
+				{
+					if (!wire->port_output)
+						continue;
+
+					for (int i = 0; i < GetSize(wire); i++)
+					{
+						SigBit wire_bit(wire, i);
+						SigBit mapped_wire_bit = sigmap(wire_bit);
+
+						if (tbuf_bits.count(mapped_wire_bit) == 0)
+							continue;
+
+						auto &tbuf_cache = tbuf_bits.at(mapped_wire_bit);
+						Cell *tbuf_cell = module->cell(tbuf_cache.first);
+
+						if (tbuf_cell == nullptr)
+							continue;
+
+						SigBit en_sig = tbuf_cell->getPort("\\E").as_bit();
+						SigBit data_sig = tbuf_cell->getPort("\\A").as_bit();
+
+						if (wire->port_input && !tinoutpad_celltype.empty())
+						{
+							log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, tinoutpad_celltype.c_str());
+
+							Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(tinoutpad_celltype));
+							Wire *owire = module->addWire(NEW_ID);
+
+							cell->setPort(RTLIL::escape_id(tinoutpad_portname), en_sig);
+							cell->setPort(RTLIL::escape_id(tinoutpad_portname2), owire);
+							cell->setPort(RTLIL::escape_id(tinoutpad_portname3), data_sig);
+							cell->setPort(RTLIL::escape_id(tinoutpad_portname4), wire_bit);
+							cell->attributes["\\keep"] = RTLIL::Const(1);
+
+							for (auto cn : tbuf_cache.second) {
+								auto c = module->cell(cn);
+								if (c == nullptr)
+									continue;
+								for (auto port : c->connections()) {
+									SigSpec sig = port.second;
+									bool newsig = false;
+									for (auto &bit : sig)
+										if (sigmap(bit) == mapped_wire_bit) {
+											bit = owire;
+											newsig = true;
+										}
+									if (newsig)
+										c->setPort(port.first, sig);
+								}
+							}
+
+
+							module->remove(tbuf_cell);
+							skip_wires[wire->name].insert(i);
+							continue;
+						}
+
+						if (!wire->port_input && !toutpad_celltype.empty())
+						{
+							log("Mapping port %s.%s[%d] using %s.\n", log_id(module), log_id(wire), i, toutpad_celltype.c_str());
+
+							Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(toutpad_celltype));
+
+							cell->setPort(RTLIL::escape_id(toutpad_portname), en_sig);
+							cell->setPort(RTLIL::escape_id(toutpad_portname2), data_sig);
+							cell->setPort(RTLIL::escape_id(toutpad_portname3), wire_bit);
+							cell->attributes["\\keep"] = RTLIL::Const(1);
+
+							for (auto cn : tbuf_cache.second) {
+								auto c = module->cell(cn);
+								if (c == nullptr)
+									continue;
+								for (auto port : c->connections()) {
+									SigSpec sig = port.second;
+									bool newsig = false;
+									for (auto &bit : sig)
+										if (sigmap(bit) == mapped_wire_bit) {
+											bit = data_sig;
+											newsig = true;
+										}
+									if (newsig)
+										c->setPort(port.first, sig);
+								}
+							}
+
+							module->remove(tbuf_cell);
+							skip_wires[wire->name].insert(i);
+							continue;
+						}
+					}
+				}
+			}
+
 			for (auto wire : module->selected_wires())
 			{
 				if (!wire->port_id)
 					continue;
 
 				std::string celltype, portname, portname2;
+				pool<int> skip_bit_indices;
+
+				if (skip_wires.count(wire->name)) {
+					if (!flag_bits)
+						continue;
+					skip_bit_indices = skip_wires.at(wire->name);
+				}
 
 				if (wire->port_input && !wire->port_output) {
 					if (inpad_celltype.empty()) {
@@ -163,12 +312,21 @@ struct IopadmapPass : public Pass {
 				if (!portname2.empty()) {
 					new_wire = module->addWire(NEW_ID, wire);
 					module->swap_names(new_wire, wire);
+					wire->attributes.clear();
 				}
 
 				if (flag_bits)
 				{
 					for (int i = 0; i < wire->width; i++)
 					{
+						if (skip_bit_indices.count(i)) {
+							if (wire->port_output)
+								module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
+							else
+								module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
+							continue;
+						}
+
 						RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
 						cell->setPort(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
 						if (!portname2.empty())
diff --git a/passes/techmap/lut2mux.cc b/passes/techmap/lut2mux.cc
index fe55e499..2bb0bd8b 100644
--- a/passes/techmap/lut2mux.cc
+++ b/passes/techmap/lut2mux.cc
@@ -67,7 +67,7 @@ struct Lut2muxPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing LUT2MUX pass (mapping to constant drivers).\n");
+		log_header(design, "Executing LUT2MUX pass (convert $lut to $_MUX_).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++)
diff --git a/passes/techmap/maccmap.cc b/passes/techmap/maccmap.cc
index d5b8fe80..32569d07 100644
--- a/passes/techmap/maccmap.cc
+++ b/passes/techmap/maccmap.cc
@@ -379,7 +379,7 @@ struct MaccmapPass : public Pass {
 	{
 		bool unmap_mode = false;
 
-		log_header("Executing MACCMAP pass (map $macc cells).\n");
+		log_header(design, "Executing MACCMAP pass (map $macc cells).\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/techmap/muxcover.cc b/passes/techmap/muxcover.cc
index 514c3365..1dc64958 100644
--- a/passes/techmap/muxcover.cc
+++ b/passes/techmap/muxcover.cc
@@ -581,7 +581,7 @@ struct MuxcoverPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing MUXCOVER pass (mapping to wider MUXes).\n");
+		log_header(design, "Executing MUXCOVER pass (mapping to wider MUXes).\n");
 
 		bool use_mux4 = false;
 		bool use_mux8 = false;
diff --git a/passes/techmap/nlutmap.cc b/passes/techmap/nlutmap.cc
index 7ece4005..6fcdf82b 100644
--- a/passes/techmap/nlutmap.cc
+++ b/passes/techmap/nlutmap.cc
@@ -26,6 +26,7 @@ PRIVATE_NAMESPACE_BEGIN
 struct NlutmapConfig
 {
 	vector<int> luts;
+	bool assert_mode = false;
 };
 
 struct NlutmapWorker
@@ -64,7 +65,7 @@ struct NlutmapWorker
 	{
 		vector<int> available_luts = config.luts;
 
-		while (!available_luts.empty())
+		while (GetSize(available_luts) > 1)
 		{
 			int n_luts = available_luts.back();
 			int lut_size = GetSize(available_luts);
@@ -84,7 +85,7 @@ struct NlutmapWorker
 				if (cell->type != "$lut" || mapped_cells.count(cell))
 					continue;
 
-				if (GetSize(cell->getPort("\\A")) == lut_size)
+				if (GetSize(cell->getPort("\\A")) == lut_size || lut_size == 2)
 					candidate_ratings[cell] = 0;
 
 				for (auto &conn : cell->connections())
@@ -116,6 +117,12 @@ struct NlutmapWorker
 				available_luts.back() += n_luts;
 		}
 
+		if (config.assert_mode) {
+			for (auto cell : module->cells())
+				if (cell->type == "$lut" && !mapped_cells.count(cell))
+					log_error("Insufficient number of LUTs to map all logic cells!\n");
+		}
+
 		run_abc(0);
 	}
 };
@@ -135,6 +142,9 @@ struct NlutmapPass : public Pass {
 		log("        The number of LUTs with 1, 2, 3, ... inputs that are\n");
 		log("        available in the target architecture.\n");
 		log("\n");
+		log("    -assert\n");
+		log("        Create an error if not all logic can be mapped\n");
+		log("\n");
 		log("Excess logic that does not fit into the specified LUTs is mapped back\n");
 		log("to generic logic gates ($_AND_, etc.).\n");
 		log("\n");
@@ -143,7 +153,7 @@ struct NlutmapPass : public Pass {
 	{
 		NlutmapConfig config;
 
-		log_header("Executing NLUTMAP pass (mapping to constant drivers).\n");
+		log_header(design, "Executing NLUTMAP pass (mapping to constant drivers).\n");
 		log_push();
 
 		size_t argidx;
@@ -156,6 +166,10 @@ struct NlutmapPass : public Pass {
 					config.luts.push_back(atoi(token.c_str()));
 				continue;
 			}
+			if (args[argidx] == "-assert") {
+				config.assert_mode = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
diff --git a/passes/techmap/pmuxtree.cc b/passes/techmap/pmuxtree.cc
index 3c12bfd0..c626dbcc 100644
--- a/passes/techmap/pmuxtree.cc
+++ b/passes/techmap/pmuxtree.cc
@@ -78,7 +78,7 @@ struct PmuxtreePass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing PMUXTREE pass.\n");
+		log_header(design, "Executing PMUXTREE pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
new file mode 100644
index 00000000..6936b499
--- /dev/null
+++ b/passes/techmap/shregmap.cc
@@ -0,0 +1,584 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#include "kernel/yosys.h"
+#include "kernel/sigtools.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ShregmapTech
+{
+	virtual ~ShregmapTech() { }
+	virtual bool analyze(vector<int> &taps) = 0;
+	virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
+};
+
+struct ShregmapOptions
+{
+	int minlen, maxlen;
+	int keep_before, keep_after;
+	bool zinit, init, params, ffe;
+	dict<IdString, pair<IdString, IdString>> ffcells;
+	ShregmapTech *tech;
+
+	ShregmapOptions()
+	{
+		minlen = 2;
+		maxlen = 0;
+		keep_before = 0;
+		keep_after = 0;
+		zinit = false;
+		init = false;
+		params = false;
+		ffe = false;
+		tech = nullptr;
+	}
+};
+
+struct ShregmapTechGreenpak4 : ShregmapTech
+{
+	bool analyze(vector<int> &taps)
+	{
+		if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
+			taps.clear();
+			return true;
+		}
+
+		if (GetSize(taps) > 2)
+			return false;
+
+		if (taps.back() > 16) return false;
+
+		return true;
+	}
+
+	bool fixup(Cell *cell, dict<int, SigBit> &taps)
+	{
+		auto D = cell->getPort("\\D");
+		auto C = cell->getPort("\\C");
+
+		auto newcell = cell->module->addCell(NEW_ID, "\\GP_SHREG");
+		newcell->setPort("\\nRST", State::S1);
+		newcell->setPort("\\CLK", C);
+		newcell->setPort("\\IN", D);
+
+		int i = 0;
+		for (auto tap : taps) {
+			newcell->setPort(i ? "\\OUTB" : "\\OUTA", tap.second);
+			newcell->setParam(i ? "\\OUTB_TAP" : "\\OUTA_TAP", tap.first + 1);
+			i++;
+		}
+
+		cell->setParam("\\OUTA_INVERT", 0);
+		return false;
+	}
+};
+
+struct ShregmapWorker
+{
+	Module *module;
+	SigMap sigmap;
+
+	const ShregmapOptions &opts;
+	int dff_count, shreg_count;
+
+	pool<Cell*> remove_cells;
+	pool<SigBit> remove_init;
+
+	dict<SigBit, bool> sigbit_init;
+	dict<SigBit, Cell*> sigbit_chain_next;
+	dict<SigBit, Cell*> sigbit_chain_prev;
+	pool<SigBit> sigbit_with_non_chain_users;
+	pool<Cell*> chain_start_cells;
+
+	void make_sigbit_chain_next_prev()
+	{
+		for (auto wire : module->wires())
+		{
+			if (wire->port_output || wire->get_bool_attribute("\\keep")) {
+				for (auto bit : sigmap(wire))
+					sigbit_with_non_chain_users.insert(bit);
+			}
+
+			if (wire->attributes.count("\\init")) {
+				SigSpec initsig = sigmap(wire);
+				Const initval = wire->attributes.at("\\init");
+				for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
+					if (initval[i] == State::S0 && !opts.zinit)
+						sigbit_init[initsig[i]] = false;
+					else if (initval[i] == State::S1)
+						sigbit_init[initsig[i]] = true;
+			}
+		}
+
+		for (auto cell : module->cells())
+		{
+			if (opts.ffcells.count(cell->type) && !cell->get_bool_attribute("\\keep"))
+			{
+				IdString d_port = opts.ffcells.at(cell->type).first;
+				IdString q_port = opts.ffcells.at(cell->type).second;
+
+				SigBit d_bit = sigmap(cell->getPort(d_port).as_bit());
+				SigBit q_bit = sigmap(cell->getPort(q_port).as_bit());
+
+				if (opts.init || sigbit_init.count(q_bit) == 0)
+				{
+					if (sigbit_chain_next.count(d_bit)) {
+						sigbit_with_non_chain_users.insert(d_bit);
+					} else
+						sigbit_chain_next[d_bit] = cell;
+
+					sigbit_chain_prev[q_bit] = cell;
+					continue;
+				}
+			}
+
+			for (auto conn : cell->connections())
+				if (cell->input(conn.first))
+					for (auto bit : sigmap(conn.second))
+						sigbit_with_non_chain_users.insert(bit);
+		}
+	}
+
+	void find_chain_start_cells()
+	{
+		for (auto it : sigbit_chain_next)
+		{
+			if (opts.tech == nullptr && sigbit_with_non_chain_users.count(it.first))
+				goto start_cell;
+
+			if (sigbit_chain_prev.count(it.first) != 0)
+			{
+				Cell *c1 = sigbit_chain_prev.at(it.first);
+				Cell *c2 = it.second;
+
+				if (c1->type != c2->type)
+					goto start_cell;
+
+				if (c1->parameters != c2->parameters)
+					goto start_cell;
+
+				IdString d_port = opts.ffcells.at(c1->type).first;
+				IdString q_port = opts.ffcells.at(c1->type).second;
+
+				auto c1_conn = c1->connections();
+				auto c2_conn = c1->connections();
+
+				c1_conn.erase(d_port);
+				c1_conn.erase(q_port);
+
+				c2_conn.erase(d_port);
+				c2_conn.erase(q_port);
+
+				if (c1_conn != c2_conn)
+					goto start_cell;
+
+				continue;
+			}
+
+		start_cell:
+			chain_start_cells.insert(it.second);
+		}
+	}
+
+	vector<Cell*> create_chain(Cell *start_cell)
+	{
+		vector<Cell*> chain;
+
+		Cell *c = start_cell;
+		while (c != nullptr)
+		{
+			chain.push_back(c);
+
+			IdString q_port = opts.ffcells.at(c->type).second;
+			SigBit q_bit = sigmap(c->getPort(q_port).as_bit());
+
+			if (sigbit_chain_next.count(q_bit) == 0)
+				break;
+
+			c = sigbit_chain_next.at(q_bit);
+			if (chain_start_cells.count(c) != 0)
+				break;
+		}
+
+		return chain;
+	}
+
+	void process_chain(vector<Cell*> &chain)
+	{
+		if (GetSize(chain) < opts.keep_before + opts.minlen + opts.keep_after)
+			return;
+
+		int cursor = opts.keep_before;
+		while (cursor < GetSize(chain) - opts.keep_after)
+		{
+			int depth = GetSize(chain) - opts.keep_after - cursor;
+
+			if (opts.maxlen > 0)
+				depth = std::min(opts.maxlen, depth);
+
+			Cell *first_cell = chain[cursor];
+			IdString q_port = opts.ffcells.at(first_cell->type).second;
+			dict<int, SigBit> taps_dict;
+
+			if (opts.tech)
+			{
+				vector<SigBit> qbits;
+				vector<int> taps;
+
+				for (int i = 0; i < depth; i++)
+				{
+					Cell *cell = chain[cursor+i];
+					auto qbit = sigmap(cell->getPort(q_port));
+					qbits.push_back(qbit);
+
+					if (sigbit_with_non_chain_users.count(qbit))
+						taps.push_back(i);
+				}
+
+				while (depth > 0)
+				{
+					if (taps.empty() || taps.back() < depth-1)
+						taps.push_back(depth-1);
+
+					if (opts.tech->analyze(taps))
+						break;
+
+					taps.pop_back();
+					depth--;
+				}
+
+				depth = 0;
+				for (auto tap : taps) {
+					taps_dict[tap] = qbits.at(tap);
+					log_assert(depth < tap+1);
+					depth = tap+1;
+				}
+			}
+
+			if (depth < 2) {
+				cursor++;
+				continue;
+			}
+
+			Cell *last_cell = chain[cursor+depth-1];
+
+			log("Converting %s.%s ... %s.%s to a shift register with depth %d.\n",
+				log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), depth);
+
+			dff_count += depth;
+			shreg_count += 1;
+
+			string shreg_cell_type_str = "$__SHREG";
+			if (opts.params) {
+				shreg_cell_type_str += "_";
+			} else {
+				if (first_cell->type[1] != '_')
+					shreg_cell_type_str += "_";
+				shreg_cell_type_str += first_cell->type.substr(1);
+			}
+
+			if (opts.init) {
+				vector<State> initval;
+				for (int i = depth-1; i >= 0; i--) {
+					SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
+					if (sigbit_init.count(bit) == 0)
+						initval.push_back(State::Sx);
+					else if (sigbit_init.at(bit))
+						initval.push_back(State::S1);
+					else
+						initval.push_back(State::S0);
+					remove_init.insert(bit);
+				}
+				first_cell->setParam("\\INIT", initval);
+			}
+
+			if (opts.zinit)
+				for (int i = depth-1; i >= 0; i--) {
+					SigBit bit = sigmap(chain[cursor+i]->getPort(q_port).as_bit());
+					remove_init.insert(bit);
+				}
+
+			if (opts.params)
+			{
+				int param_clkpol = -1;
+				int param_enpol = 2;
+
+				if (first_cell->type == "$_DFF_N_") param_clkpol = 0;
+				if (first_cell->type == "$_DFF_P_") param_clkpol = 1;
+
+				if (first_cell->type == "$_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
+				if (first_cell->type == "$_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
+				if (first_cell->type == "$_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
+				if (first_cell->type == "$_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
+
+				log_assert(param_clkpol >= 0);
+				first_cell->setParam("\\CLKPOL", param_clkpol);
+				if (opts.ffe) first_cell->setParam("\\ENPOL", param_enpol);
+			}
+
+			first_cell->type = shreg_cell_type_str;
+			first_cell->setPort(q_port, last_cell->getPort(q_port));
+			first_cell->setParam("\\DEPTH", depth);
+
+			if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
+				remove_cells.insert(first_cell);
+
+			for (int i = 1; i < depth; i++)
+				remove_cells.insert(chain[cursor+i]);
+			cursor += depth;
+		}
+	}
+
+	void cleanup()
+	{
+		for (auto cell : remove_cells)
+			module->remove(cell);
+
+		for (auto wire : module->wires())
+		{
+			if (wire->attributes.count("\\init") == 0)
+				continue;
+
+			SigSpec initsig = sigmap(wire);
+			Const &initval = wire->attributes.at("\\init");
+
+			for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
+				if (remove_init.count(initsig[i]))
+					initval[i] = State::Sx;
+
+			if (SigSpec(initval).is_fully_undef())
+				wire->attributes.erase("\\init");
+		}
+
+		remove_cells.clear();
+		sigbit_chain_next.clear();
+		sigbit_chain_prev.clear();
+		chain_start_cells.clear();
+	}
+
+	ShregmapWorker(Module *module, const ShregmapOptions &opts) :
+			module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
+	{
+		make_sigbit_chain_next_prev();
+		find_chain_start_cells();
+
+		for (auto c : chain_start_cells) {
+			vector<Cell*> chain = create_chain(c);
+			process_chain(chain);
+		}
+
+		cleanup();
+	}
+};
+
+struct ShregmapPass : public Pass {
+	ShregmapPass() : Pass("shregmap", "map shift registers") { }
+	virtual void help()
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    shregmap [options] [selection]\n");
+		log("\n");
+		log("This pass converts chains of $_DFF_[NP]_ gates to target specific shift register\n");
+		log("primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and\n");
+		log("will use the same interface as the original $_DFF_*_ cells. The cell parameter\n");
+		log("'DEPTH' will contain the depth of the shift register. Use a target-specific\n");
+		log("'techmap' map file to convert those cells to the actual target cells.\n");
+		log("\n");
+		log("    -minlen N\n");
+		log("        minimum length of shift register (default = 2)\n");
+		log("        (this is the length after -keep_before and -keep_after)\n");
+		log("\n");
+		log("    -maxlen N\n");
+		log("        maximum length of shift register (default = no limit)\n");
+		log("        larger chains will be mapped to multiple shift register instances\n");
+		log("\n");
+		log("    -keep_before N\n");
+		log("        number of DFFs to keep before the shift register (default = 0)\n");
+		log("\n");
+		log("    -keep_after N\n");
+		log("        number of DFFs to keep after the shift register (default = 0)\n");
+		log("\n");
+		log("    -clkpol pos|neg|any\n");
+		log("        limit match to only positive or negative edge clocks. (default = any)\n");
+		log("\n");
+		log("    -enpol pos|neg|none|any_or_none|any\n");
+		log("        limit match to FFs with the specified enable polarity. (default = none)\n");
+		log("\n");
+		log("    -match <cell_type>[:<d_port_name>:<q_port_name>]\n");
+		log("        match the specified cells instead of $_DFF_N_ and $_DFF_P_. If\n");
+		log("        ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used\n");
+		log("        by default. E.g. the option '-clkpol pos' is just an alias for\n");
+		log("        '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.\n");
+		log("\n");
+		log("    -params\n");
+		log("        instead of encoding the clock and enable polarity in the cell name by\n");
+		log("        deriving from the original cell name, simply name all generated cells\n");
+		log("        $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is\n");
+		log("        used to denote cells without enable input. The ENPOL parameter is\n");
+		log("        omitted when '-enpol none' (or no -enpol option) is passed.\n");
+		log("\n");
+		log("    -zinit\n");
+		log("        assume the shift register is automatically zero-initialized, so it\n");
+		log("        becomes legal to merge zero initialized FFs into the shift register.\n");
+		log("\n");
+		log("    -init\n");
+		log("        map initialized registers to the shift reg, add an INIT parameter to\n");
+		log("        generated cells with the initialization value. (first bit to shift out\n");
+		log("        in LSB position)\n");
+		log("\n");
+		log("    -tech greenpak4\n");
+		log("        map to greenpak4 shift registers.\n");
+		log("\n");
+	}
+	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
+	{
+		ShregmapOptions opts;
+		string clkpol, enpol;
+
+		log_header(design, "Executing SHREGMAP pass (map shift registers).\n");
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-clkpol" && argidx+1 < args.size()) {
+				clkpol = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-enpol" && argidx+1 < args.size()) {
+				enpol = args[++argidx];
+				continue;
+			}
+			if (args[argidx] == "-match" && argidx+1 < args.size()) {
+				vector<string> match_args = split_tokens(args[++argidx], ":");
+				if (GetSize(match_args) < 2)
+					match_args.push_back("D");
+				if (GetSize(match_args) < 3)
+					match_args.push_back("Q");
+				IdString id_cell_type(RTLIL::escape_id(match_args[0]));
+				IdString id_d_port_name(RTLIL::escape_id(match_args[1]));
+				IdString id_q_port_name(RTLIL::escape_id(match_args[2]));
+				opts.ffcells[id_cell_type] = make_pair(id_d_port_name, id_q_port_name);
+				continue;
+			}
+			if (args[argidx] == "-minlen" && argidx+1 < args.size()) {
+				opts.minlen = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-maxlen" && argidx+1 < args.size()) {
+				opts.maxlen = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-keep_before" && argidx+1 < args.size()) {
+				opts.keep_before = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-keep_after" && argidx+1 < args.size()) {
+				opts.keep_after = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-tech" && argidx+1 < args.size() && opts.tech == nullptr) {
+				string tech = args[++argidx];
+				if (tech == "greenpak4") {
+					clkpol = "pos";
+					opts.zinit = true;
+					opts.tech = new ShregmapTechGreenpak4;
+				} else {
+					argidx--;
+					break;
+				}
+				continue;
+			}
+			if (args[argidx] == "-zinit") {
+				opts.zinit = true;
+				continue;
+			}
+			if (args[argidx] == "-init") {
+				opts.init = true;
+				continue;
+			}
+			if (args[argidx] == "-params") {
+				opts.params = true;
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design);
+
+		if (opts.zinit && opts.init)
+			log_cmd_error("Options -zinit and -init are exclusive!\n");
+
+		if (opts.ffcells.empty())
+		{
+			bool clk_pos = clkpol == "" || clkpol == "pos" || clkpol == "any";
+			bool clk_neg = clkpol == "" || clkpol == "neg" || clkpol == "any";
+
+			bool en_none = enpol == "" || enpol == "none" || enpol == "any_or_none";
+			bool en_pos = enpol == "pos" || enpol == "any" || enpol == "any_or_none";
+			bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
+
+			if (clk_pos && en_none)
+				opts.ffcells["$_DFF_P_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+			if (clk_neg && en_none)
+				opts.ffcells["$_DFF_N_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+
+			if (clk_pos && en_pos)
+				opts.ffcells["$_DFFE_PP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+			if (clk_pos && en_neg)
+				opts.ffcells["$_DFFE_PN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+
+			if (clk_neg && en_pos)
+				opts.ffcells["$_DFFE_NP_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+			if (clk_neg && en_neg)
+				opts.ffcells["$_DFFE_NN_"] = make_pair(IdString("\\D"), IdString("\\Q"));
+
+			if (en_pos || en_neg)
+				opts.ffe = true;
+		}
+		else
+		{
+			if (!clkpol.empty())
+				log_cmd_error("Options -clkpol and -match are exclusive!\n");
+			if (!enpol.empty())
+				log_cmd_error("Options -enpol and -match are exclusive!\n");
+			if (opts.params)
+				log_cmd_error("Options -params and -match are exclusive!\n");
+		}
+
+		int dff_count = 0;
+		int shreg_count = 0;
+
+		for (auto module : design->selected_modules()) {
+			ShregmapWorker worker(module, opts);
+			dff_count += worker.dff_count;
+			shreg_count += worker.shreg_count;
+		}
+
+		log("Converted %d dff cells into %d shift registers.\n", dff_count, shreg_count);
+
+		if (opts.tech != nullptr) {
+			delete opts.tech;
+			opts.tech = nullptr;
+		}
+	}
+} ShregmapPass;
+
+PRIVATE_NAMESPACE_END
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f6ac3964..0fb64734 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -321,6 +321,36 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
 	module->connect(cell->getPort("\\Y"), lut_data);
 }
 
+void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+	SigSpec ctrl = cell->getPort("\\A");
+	SigSpec table = cell->getParam("\\TABLE");
+
+	int width = cell->getParam("\\WIDTH").as_int();
+	int depth = cell->getParam("\\DEPTH").as_int();
+	table.extend_u0(2 * width * depth);
+
+	SigSpec products;
+
+	for (int i = 0; i < depth; i++) {
+		SigSpec in, pat;
+		for (int j = 0; j < width; j++) {
+			if (table[2*i*width + 2*j + 0] == State::S1) {
+				in.append(ctrl[j]);
+				pat.append(State::S0);
+			}
+			if (table[2*i*width + 2*j + 1] == State::S1) {
+				in.append(ctrl[j]);
+				pat.append(State::S1);
+			}
+		}
+
+		products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
+	}
+
+	module->connect(cell->getPort("\\Y"), module->ReduceOr(NEW_ID, products));
+}
+
 void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
 {
 	int offset = cell->parameters.at("\\OFFSET").as_int();
@@ -498,6 +528,7 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
 	mappers["$mux"]         = simplemap_mux;
 	mappers["$tribuf"]      = simplemap_tribuf;
 	mappers["$lut"]         = simplemap_lut;
+	mappers["$sop"]         = simplemap_sop;
 	mappers["$slice"]       = simplemap_slice;
 	mappers["$concat"]      = simplemap_concat;
 	mappers["$sr"]          = simplemap_sr;
@@ -543,7 +574,7 @@ struct SimplemapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
+		log_header(design, "Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 		extra_args(args, 1, design);
 
 		std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 5334ebfa..b2cc492b 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -234,8 +234,10 @@ struct TechmapWorker
 				tpl_written_bits.insert(bit);
 
 		SigMap port_signal_map;
+		SigSig port_signal_assign;
 
-		for (auto &it : cell->connections()) {
+		for (auto &it : cell->connections())
+		{
 			RTLIL::IdString portname = it.first;
 			if (positional_ports.count(portname) > 0)
 				portname = positional_ports.at(portname);
@@ -244,16 +246,22 @@ struct TechmapWorker
 					log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
 				continue;
 			}
+
 			RTLIL::Wire *w = tpl->wires_.at(portname);
-			RTLIL::SigSig c;
+			RTLIL::SigSig c, extra_connect;
+
 			if (w->port_output && !w->port_input) {
 				c.first = it.second;
 				c.second = RTLIL::SigSpec(w);
 				apply_prefix(cell->name.str(), c.second, module);
+				extra_connect.first = c.second;
+				extra_connect.second = c.first;
 			} else if (!w->port_output && w->port_input) {
 				c.first = RTLIL::SigSpec(w);
 				c.second = it.second;
 				apply_prefix(cell->name.str(), c.first, module);
+				extra_connect.first = c.first;
+				extra_connect.second = c.second;
 			} else {
 				SigSpec sig_tpl = w, sig_tpl_pf = w, sig_mod = it.second;
 				apply_prefix(cell->name.str(), sig_tpl_pf, module);
@@ -266,28 +274,48 @@ struct TechmapWorker
 						c.second.append(sig_mod[i]);
 					}
 				}
+				extra_connect.first = sig_tpl_pf;
+				extra_connect.second = sig_mod;
 			}
+
 			if (c.second.size() > c.first.size())
 				c.second.remove(c.first.size(), c.second.size() - c.first.size());
+
 			if (c.second.size() < c.first.size())
 				c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
+
 			log_assert(c.first.size() == c.second.size());
-			if (flatten_mode) {
+
+			if (flatten_mode)
+			{
 				// more conservative approach:
 				// connect internal and external wires
+
 				if (sigmaps.count(module) == 0)
 					sigmaps[module].set(module);
+
 				if (sigmaps.at(module)(c.first).has_const())
 					log_error("Mismatch in directionality for cell port %s.%s.%s: %s <= %s\n",
 						log_id(module), log_id(cell), log_id(it.first), log_signal(c.first), log_signal(c.second));
+
 				module->connect(c);
-			} else {
+			}
+			else
+			{
 				// approach that yields nicer outputs:
 				// replace internal wires that are connected to external wires
+
 				if (w->port_output)
 					port_signal_map.add(c.second, c.first);
 				else
 					port_signal_map.add(c.first, c.second);
+
+				for (auto &attr : w->attributes) {
+					if (attr.first == "\\src")
+						continue;
+					module->connect(extra_connect);
+					break;
+				}
 			}
 		}
 
@@ -611,7 +639,7 @@ struct TechmapWorker
 					if (techmap_cache.count(key) > 0) {
 						tpl = techmap_cache[key];
 					} else {
-						if (cell->parameters.size() != 0) {
+						if (parameters.size() != 0) {
 							derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
 							tpl = map->module(derived_name);
 							log_continue = true;
@@ -779,7 +807,7 @@ struct TechmapWorker
 
 					if (recursive_mode) {
 						if (log_continue) {
-							log_header("Continuing TECHMAP pass.\n");
+							log_header(design, "Continuing TECHMAP pass.\n");
 							log_continue = false;
 						}
 						while (techmap_module(map, tpl, map, handled_cells, celltypeMap, true)) { }
@@ -790,7 +818,7 @@ struct TechmapWorker
 					continue;
 
 				if (log_continue) {
-					log_header("Continuing TECHMAP pass.\n");
+					log_header(design, "Continuing TECHMAP pass.\n");
 					log_continue = false;
 				}
 
@@ -833,7 +861,7 @@ struct TechmapWorker
 		}
 
 		if (log_continue) {
-			log_header("Continuing TECHMAP pass.\n");
+			log_header(design, "Continuing TECHMAP pass.\n");
 			log_continue = false;
 		}
 
@@ -976,7 +1004,7 @@ struct TechmapPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing TECHMAP pass (map to technology primitives).\n");
+		log_header(design, "Executing TECHMAP pass (map to technology primitives).\n");
 		log_push();
 
 		TechmapWorker worker;
@@ -1108,7 +1136,7 @@ struct FlattenPass : public Pass {
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
-		log_header("Executing FLATTEN pass (flatten design).\n");
+		log_header(design, "Executing FLATTEN pass (flatten design).\n");
 		log_push();
 
 		extra_args(args, 1, design);
diff --git a/passes/techmap/tribuf.cc b/passes/techmap/tribuf.cc
index d0564b4e..03629082 100644
--- a/passes/techmap/tribuf.cc
+++ b/passes/techmap/tribuf.cc
@@ -160,7 +160,7 @@ struct TribufPass : public Pass {
 	{
 		TribufConfig config;
 
-		log_header("Executing TRIBUF pass.\n");
+		log_header(design, "Executing TRIBUF pass.\n");
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {