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-rw-r--r--passes/techmap/Makefile.inc3
-rw-r--r--passes/techmap/techmap.cc4
2 files changed, 4 insertions, 3 deletions
diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index ba365525..97023625 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -3,8 +3,9 @@ GENFILES += passes/techmap/stdcells.inc
OBJS += passes/techmap/techmap.o
passes/techmap/stdcells.inc: techlibs/stdcells.v
+ echo "// autogenerated from $<" > $@.new
od -v -td1 -w1 $< | awk 'BEGIN { print "static char stdcells_code[] = {"; } $$2 != "" { print $$2 ","; } \
- END { print 0 "};"; }' | fmt > $@.new
+ END { print 0 "};"; }' | fmt >> $@.new
mv $@.new $@
passes/techmap/techmap.o: passes/techmap/stdcells.inc
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index c05a96cd..5fd5858a 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -172,14 +172,14 @@ struct TechmapPass : public Pass {
log("\n");
log(" techmap [-map filename] [selection]\n");
log("\n");
- log("This pass implements a very simple technology mapper than replaces cells in\n");
+ log("This pass implements a very simple technology mapper that replaces cells in\n");
log("the design with implementations given in form of a verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log(" the library of cell implementations to be used.\n");
log(" without this parameter a builtin library is used that\n");
- log(" transform the internal RTL cells to the internal gate\n");
+ log(" transforms the internal RTL cells to the internal gate\n");
log(" library.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");