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-rw-r--r--passes/cmds/delete.cc8
-rw-r--r--passes/cmds/rename.cc8
-rw-r--r--passes/cmds/select.cc4
-rw-r--r--passes/cmds/setattr.cc2
-rw-r--r--passes/cmds/splitnets.cc2
-rw-r--r--passes/fsm/fsm_export.cc4
-rw-r--r--passes/hierarchy/hierarchy.cc4
-rw-r--r--passes/opt/opt_clean.cc2
-rw-r--r--passes/opt/opt_const.cc6
-rw-r--r--passes/opt/opt_share.cc18
-rw-r--r--passes/opt/wreduce.cc4
-rw-r--r--passes/techmap/extract.cc4
-rw-r--r--passes/techmap/techmap.cc8
13 files changed, 39 insertions, 35 deletions
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 8c3391e5..d7edcfbf 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -91,10 +91,10 @@ struct DeletePass : public Pass {
continue;
}
- std::set<RTLIL::Wire*> delete_wires;
- std::set<RTLIL::Cell*> delete_cells;
- std::set<RTLIL::IdString> delete_procs;
- std::set<RTLIL::IdString> delete_mems;
+ nodict<RTLIL::Wire*> delete_wires;
+ nodict<RTLIL::Cell*> delete_cells;
+ nodict<RTLIL::IdString> delete_procs;
+ nodict<RTLIL::IdString> delete_mems;
for (auto &it : module->wires_)
if (design->selected(module, it.second))
diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index b2e10e55..8f24af27 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -118,7 +118,7 @@ struct RenamePass : public Pass {
if (!design->selected(module))
continue;
- std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+ dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
for (auto &it : module->wires_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@@ -128,7 +128,7 @@ struct RenamePass : public Pass {
module->wires_.swap(new_wires);
module->fixup_ports();
- std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+ dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
if (it.first[0] == '$' && design->selected(module, it.second))
do it.second->name = stringf("\\%s%d%s", pattern_prefix.c_str(), counter++, pattern_suffix.c_str());
@@ -149,7 +149,7 @@ struct RenamePass : public Pass {
if (!design->selected(module))
continue;
- std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+ dict<RTLIL::IdString, RTLIL::Wire*> new_wires;
for (auto &it : module->wires_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\' && it.second->port_id == 0)
@@ -159,7 +159,7 @@ struct RenamePass : public Pass {
module->wires_.swap(new_wires);
module->fixup_ports();
- std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+ dict<RTLIL::IdString, RTLIL::Cell*> new_cells;
for (auto &it : module->cells_) {
if (design->selected(module, it.second))
if (it.first[0] == '\\')
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index 7f841673..91368f57 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -101,7 +101,7 @@ static bool match_attr_val(const RTLIL::Const &value, std::string pattern, char
log_abort();
}
-static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
+static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string name_pat, std::string value_pat, char match_op)
{
if (name_pat.find('*') != std::string::npos || name_pat.find('?') != std::string::npos || name_pat.find('[') != std::string::npos) {
for (auto &it : attributes) {
@@ -119,7 +119,7 @@ static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes
return false;
}
-static bool match_attr(const std::map<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
+static bool match_attr(const dict<RTLIL::IdString, RTLIL::Const> &attributes, std::string match_expr)
{
size_t pos = match_expr.find_first_of("<!=>");
diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
index 39c75c54..9a6d8a03 100644
--- a/passes/cmds/setattr.cc
+++ b/passes/cmds/setattr.cc
@@ -50,7 +50,7 @@ struct setunset_t
}
};
-static void do_setunset(std::map<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
+static void do_setunset(dict<RTLIL::IdString, RTLIL::Const> &attrs, std::vector<setunset_t> &list)
{
for (auto &item : list)
if (item.unset)
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index a6c9fe88..6c24a8e5 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -176,7 +176,7 @@ struct SplitnetsPass : public Pass {
module->rewrite_sigspecs(worker);
- std::set<RTLIL::Wire*> delete_wires;
+ nodict<RTLIL::Wire*> delete_wires;
for (auto &it : worker.splitmap)
delete_wires.insert(it.first);
module->remove(delete_wires);
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index 668fe8d1..ad927033 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -50,7 +50,7 @@ std::string kiss_convert_signal(const RTLIL::SigSpec &sig) {
* @param cell pointer to the FSM cell which should be exported.
*/
void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::string filename, bool origenc) {
- std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
+ dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
FsmData fsm_data;
FsmData::transition_t tr;
std::ofstream kiss_file;
@@ -145,7 +145,7 @@ struct FsmExportPass : public Pass {
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
- std::map<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
+ dict<RTLIL::IdString, RTLIL::Const>::iterator attr_it;
std::string arg;
bool flag_noauto = false;
std::string filename;
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index e95947a9..66d66032 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -462,7 +462,7 @@ struct HierarchyPass : public Pass {
log_cmd_error("Option -top requires an additional argument!\n");
top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) {
- std::map<RTLIL::IdString, RTLIL::Const> empty_parameters;
+ dict<RTLIL::IdString, RTLIL::Const> empty_parameters;
design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters);
top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL;
}
@@ -560,7 +560,7 @@ struct HierarchyPass : public Pass {
RTLIL::Cell *cell = work.second;
log("Mapping positional arguments of cell %s.%s (%s).\n",
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
- std::map<RTLIL::IdString, RTLIL::SigSpec> new_connections;
+ dict<RTLIL::IdString, RTLIL::SigSpec> new_connections;
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
int id = atoi(conn.first.c_str()+1);
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 8a20898c..01acb5c0 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -262,7 +262,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
}
- std::set<RTLIL::Wire*> del_wires;
+ nodict<RTLIL::Wire*> del_wires;
int del_wires_count = 0;
for (auto wire : maybe_del_wires)
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 5bac76cf..7f800bde 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -196,11 +196,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
ct_combinational.setup_stdcells();
SigMap assign_map(module);
- std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
+ dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
- std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
- std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
+ dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
+ dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->cells())
if (design->selected(module, cell) && cell->type[0] == '$') {
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index f8bc0220..c581b749 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -41,7 +41,7 @@ struct OptShareWorker
CellTypes ct;
int total_count;
#ifdef USE_CELL_HASH_CACHE
- std::map<const RTLIL::Cell*, std::string> cell_hash_cache;
+ dict<const RTLIL::Cell*, std::string> cell_hash_cache;
#endif
#ifdef USE_CELL_HASH_CACHE
@@ -67,8 +67,8 @@ struct OptShareWorker
for (auto &it : cell->parameters)
hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
- const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
- std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
+ const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
+ dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
@@ -127,12 +127,14 @@ struct OptShareWorker
#endif
if (cell1->parameters != cell2->parameters) {
- lt = cell1->parameters < cell2->parameters;
+ std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
+ std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
+ lt = p1 < p2;
return true;
}
- std::map<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
- std::map<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
+ dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
+ dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
for (auto &it : conn1) {
if (ct.cell_output(cell1->type, it.first))
@@ -171,7 +173,9 @@ struct OptShareWorker
}
if (conn1 != conn2) {
- lt = conn1 < conn2;
+ std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
+ std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
+ lt = c1 < c2;
return true;
}
diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index 8f59a041..e8a38d21 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -28,11 +28,11 @@ PRIVATE_NAMESPACE_BEGIN
struct WreduceConfig
{
- std::set<IdString> supported_cell_types;
+ nodict<IdString> supported_cell_types;
WreduceConfig()
{
- supported_cell_types = std::set<IdString>({
+ supported_cell_types = nodict<IdString>({
"$not", "$pos", "$neg",
"$and", "$or", "$xor", "$xnor",
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 994ef8f2..ff99040e 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -42,7 +42,7 @@ public:
{
}
- bool compareAttributes(const std::set<RTLIL::IdString> &attr, const std::map<RTLIL::IdString, RTLIL::Const> &needleAttr, const std::map<RTLIL::IdString, RTLIL::Const> &haystackAttr)
+ bool compareAttributes(const std::set<RTLIL::IdString> &attr, const dict<RTLIL::IdString, RTLIL::Const> &needleAttr, const dict<RTLIL::IdString, RTLIL::Const> &haystackAttr)
{
for (auto &it : attr) {
size_t nc = needleAttr.count(it), hc = haystackAttr.count(it);
@@ -123,7 +123,7 @@ public:
{
RTLIL::Wire *lastNeedleWire = NULL;
RTLIL::Wire *lastHaystackWire = NULL;
- std::map<RTLIL::IdString, RTLIL::Const> emptyAttr;
+ dict<RTLIL::IdString, RTLIL::Const> emptyAttr;
for (auto &conn : needleCell->connections())
{
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 04d345d3..94dd4d42 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -341,7 +341,7 @@ struct TechmapWorker
{
RTLIL::IdString derived_name = tpl_name;
RTLIL::Module *tpl = map->modules_[tpl_name];
- std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
+ std::map<RTLIL::IdString, RTLIL::Const> parameters(cell->parameters.begin(), cell->parameters.end());
if (tpl->get_bool_attribute("\\blackbox"))
continue;
@@ -529,7 +529,7 @@ struct TechmapWorker
tpl = techmap_cache[key];
} else {
if (cell->parameters.size() != 0) {
- derived_name = tpl->derive(map, parameters);
+ derived_name = tpl->derive(map, dict<RTLIL::IdString, RTLIL::Const>(parameters.begin(), parameters.end()));
tpl = map->module(derived_name);
log_continue = true;
}
@@ -975,7 +975,7 @@ struct TechmapPass : public Pass {
Frontend::frontend_call(map, &f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
}
- std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
+ dict<RTLIL::IdString, RTLIL::Module*> modules_new;
for (auto &it : map->modules_) {
if (it.first.substr(0, 2) == "\\$")
it.second->name = it.first.substr(1);
@@ -1072,7 +1072,7 @@ struct FlattenPass : public Pass {
log("No more expansions possible.\n");
if (top_mod != NULL) {
- std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
+ dict<RTLIL::IdString, RTLIL::Module*> new_modules;
for (auto mod : design->modules())
if (mod == top_mod || mod->get_bool_attribute("\\blackbox")) {
new_modules[mod->name] = mod;
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-04 00:17:46 +0000