diff options
Diffstat (limited to 'passes')
57 files changed, 169 insertions, 169 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 7ba9424e..03fc9f93 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -684,7 +684,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std free(p); log_header("Re-integrating ABC results.\n"); - RTLIL::Module *mapped_mod = mapped_design->modules["\\netlist"]; + RTLIL::Module *mapped_mod = mapped_design->modules_["\\netlist"]; if (mapped_mod == NULL) log_error("ABC output file does not contain a module `netlist'.\n"); for (auto &it : mapped_mod->wires_) { @@ -1000,7 +1000,7 @@ struct AbcPass : public Pass { if (!constr_file.empty() && liberty_file.empty()) log_cmd_error("Got -constr but no -liberty!\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (mod_it.second->processes.size() > 0) log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str()); diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc index 773bbe5d..4bcbc013 100644 --- a/passes/abc/blifparse.cc +++ b/passes/abc/blifparse.cc @@ -60,7 +60,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name) int port_count = 0; module->name = "\\netlist"; - design->modules[module->name] = module; + design->modules_[module->name] = module; size_t buffer_size = 4096; char *buffer = (char*)malloc(buffer_size); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 49aa7c98..62995a49 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -64,10 +64,10 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n for (auto &it : module->cells_) { - if (design->modules.count(it.second->type) == 0) + if (design->modules_.count(it.second->type) == 0) continue; - RTLIL::Module *mod = design->modules.at(it.second->type); + RTLIL::Module *mod = design->modules_.at(it.second->type); if (!design->selected_whole_module(mod->name)) continue; if (mod->get_bool_attribute("\\blackbox")) @@ -136,7 +136,7 @@ struct AddPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; if (!design->selected_whole_module(module->name)) diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 6494ea6f..3e13fd4d 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -75,7 +75,7 @@ struct ConnectPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { RTLIL::Module *module = NULL; - for (auto &it : design->modules) { + for (auto &it : design->modules_) { if (!design->selected(it.second)) continue; if (module != NULL) diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index cc8147c5..5125ff5e 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -197,7 +197,7 @@ struct ConnwrappersPass : public Pass { log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) worker.work(design, mod_it.second); } diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index 4b1a8db8..fc801f61 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -41,14 +41,14 @@ struct CopyPass : public Pass { std::string src_name = RTLIL::escape_id(args[1]); std::string trg_name = RTLIL::escape_id(args[2]); - if (design->modules.count(src_name) == 0) + if (design->modules_.count(src_name) == 0) log_cmd_error("Can't find source module %s.\n", src_name.c_str()); - if (design->modules.count(trg_name) != 0) + if (design->modules_.count(trg_name) != 0) log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); - design->modules[trg_name] = design->modules.at(src_name)->clone(); - design->modules[trg_name]->name = trg_name; + design->modules_[trg_name] = design->modules_.at(src_name)->clone(); + design->modules_[trg_name]->name = trg_name; } } CopyPass; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 2c2c370d..67b4d939 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -66,7 +66,7 @@ struct DeletePass : public Pass { std::vector<std::string> delete_mods; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (design->selected_whole_module(mod_it.first) && !flag_input && !flag_output) { delete_mods.push_back(mod_it.first); @@ -134,8 +134,8 @@ struct DeletePass : public Pass { } for (auto &it : delete_mods) { - delete design->modules.at(it); - design->modules.erase(it); + delete design->modules_.at(it); + design->modules_.erase(it); } } } DeletePass; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 7b8889d6..bd1ee68f 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -165,7 +165,7 @@ struct DesignPass : public Pass { argidx = args.size(); } - for (auto &it : copy_from_design->modules) { + for (auto &it : copy_from_design->modules_) { if (sel.selected_whole_module(it.first)) { copy_src_modules.push_back(it.second); continue; @@ -192,10 +192,10 @@ struct DesignPass : public Pass { { std::string trg_name = as_name.empty() ? mod->name : RTLIL::escape_id(as_name); - if (copy_to_design->modules.count(trg_name)) - delete copy_to_design->modules.at(trg_name); - copy_to_design->modules[trg_name] = mod->clone(); - copy_to_design->modules[trg_name]->name = trg_name; + if (copy_to_design->modules_.count(trg_name)) + delete copy_to_design->modules_.at(trg_name); + copy_to_design->modules_[trg_name] = mod->clone(); + copy_to_design->modules_[trg_name]->name = trg_name; } } @@ -203,8 +203,8 @@ struct DesignPass : public Pass { { RTLIL::Design *design_copy = new RTLIL::Design; - for (auto &it : design->modules) - design_copy->modules[it.first] = it.second->clone(); + for (auto &it : design->modules_) + design_copy->modules_[it.first] = it.second->clone(); design_copy->selection_stack = design->selection_stack; design_copy->selection_vars = design->selection_vars; @@ -221,9 +221,9 @@ struct DesignPass : public Pass { if (reset_mode || !load_name.empty() || push_mode || pop_mode) { - for (auto &it : design->modules) + for (auto &it : design->modules_) delete it.second; - design->modules.clear(); + design->modules_.clear(); design->selection_stack.clear(); design->selection_vars.clear(); @@ -239,8 +239,8 @@ struct DesignPass : public Pass { if (pop_mode) pushed_designs.pop_back(); - for (auto &it : saved_design->modules) - design->modules[it.first] = it.second->clone(); + for (auto &it : saved_design->modules_) + design->modules_[it.first] = it.second->clone(); design->selection_stack = saved_design->selection_stack; design->selection_vars = saved_design->selection_vars; diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index c8b8160f..3a600872 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -96,7 +96,7 @@ struct RenamePass : public Pass { { extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { int counter = 0; @@ -128,7 +128,7 @@ struct RenamePass : public Pass { { extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; if (!design->selected(module)) @@ -163,19 +163,19 @@ struct RenamePass : public Pass { if (!design->selected_active_module.empty()) { - if (design->modules.count(design->selected_active_module) > 0) - rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name); + if (design->modules_.count(design->selected_active_module) > 0) + rename_in_module(design->modules_.at(design->selected_active_module), from_name, to_name); } else { - for (auto &mod : design->modules) { + for (auto &mod : design->modules_) { if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) { to_name = RTLIL::escape_id(to_name); log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str()); RTLIL::Module *module = mod.second; - design->modules.erase(module->name); + design->modules_.erase(module->name); module->name = to_name; - design->modules[module->name] = module; + design->modules_[module->name] = module; goto rename_ok; } } diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index a1c12f1e..e09c0012 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -43,7 +43,7 @@ struct ScatterPass : public Pass { CellTypes ct(design); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index c9504341..1fa1b4c9 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -280,7 +280,7 @@ struct SccPass : public Pass { RTLIL::Selection newSelection(false); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { SccWorker worker(design, mod_it.second, allCellTypes, maxDepth); diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 306b7a5b..85c52277 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -151,7 +151,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) RTLIL::Selection new_sel(false); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first)) continue; @@ -181,13 +181,13 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first)) { for (auto &cell_it : mod_it.second->cells_) { - if (design->modules.count(cell_it.second->type) == 0) + if (design->modules_.count(cell_it.second->type) == 0) continue; lhs.selected_modules.insert(cell_it.second->type); } @@ -205,7 +205,7 @@ static void select_op_fullmod(RTLIL::Design *design, RTLIL::Selection &lhs) static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs) { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first)) continue; @@ -260,7 +260,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R if (!rhs.full_selection && rhs.selected_modules.size() == 0 && rhs.selected_members.size() == 0) return; lhs.full_selection = false; - for (auto &it : design->modules) + for (auto &it : design->modules_) lhs.selected_modules.insert(it.first); } @@ -271,10 +271,10 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R for (auto &it : rhs.selected_members) { - if (design->modules.count(it.first) == 0) + if (design->modules_.count(it.first) == 0) continue; - RTLIL::Module *mod = design->modules[it.first]; + RTLIL::Module *mod = design->modules_[it.first]; if (lhs.selected_modules.count(mod->name) > 0) { @@ -304,7 +304,7 @@ static void select_op_intersect(RTLIL::Design *design, RTLIL::Selection &lhs, co if (lhs.full_selection) { lhs.full_selection = false; - for (auto &it : design->modules) + for (auto &it : design->modules_) lhs.selected_modules.insert(it.first); } @@ -368,7 +368,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v { int sel_objects = 0; bool is_input, is_output; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (lhs.selected_whole_module(mod_it.first) || !lhs.selected_module(mod_it.first)) continue; @@ -684,7 +684,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) } sel.full_selection = false; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (arg_mod.substr(0, 2) == "A:") { if (!match_attr(mod_it.second->attributes, arg_mod.substr(2))) @@ -1078,7 +1078,7 @@ struct SelectPass : public Pass { } if (arg == "-module" && argidx+1 < args.size()) { RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]); - if (design->modules.count(mod_name) == 0) + if (design->modules_.count(mod_name) == 0) log_cmd_error("No such module: %s\n", id2cstr(mod_name)); design->selected_active_module = mod_name; got_module = true; @@ -1147,7 +1147,7 @@ struct SelectPass : public Pass { if (work_stack.size() > 0) sel = &work_stack.back(); sel->optimize(design); - for (auto mod_it : design->modules) + for (auto mod_it : design->modules_) { if (sel->selected_whole_module(mod_it.first) && list_mode) log("%s\n", id2cstr(mod_it.first)); @@ -1217,7 +1217,7 @@ struct SelectPass : public Pass { log_cmd_error("No selection to check.\n"); RTLIL::Selection *sel = &work_stack.back(); sel->optimize(design); - for (auto mod_it : design->modules) + for (auto mod_it : design->modules_) if (sel->selected_module(mod_it.first)) { for (auto &it : mod_it.second->wires_) if (sel->selected_member(mod_it.first, it.first)) @@ -1299,15 +1299,15 @@ struct CdPass : public Pass { std::string modname = RTLIL::escape_id(args[1]); - if (design->modules.count(modname) == 0 && !design->selected_active_module.empty()) { + if (design->modules_.count(modname) == 0 && !design->selected_active_module.empty()) { RTLIL::Module *module = NULL; - if (design->modules.count(design->selected_active_module) > 0) - module = design->modules.at(design->selected_active_module); + if (design->modules_.count(design->selected_active_module) > 0) + module = design->modules_.at(design->selected_active_module); if (module != NULL && module->cells_.count(modname) > 0) modname = module->cells_.at(modname)->type; } - if (design->modules.count(modname) > 0) { + if (design->modules_.count(modname) > 0) { design->selected_active_module = modname; design->selection_stack.back() = RTLIL::Selection(); select_filter_active_mod(design, design->selection_stack.back()); @@ -1368,12 +1368,12 @@ struct LsPass : public Pass { if (design->selected_active_module.empty()) { - counter += log_matches("modules", pattern, design->modules); + counter += log_matches("modules", pattern, design->modules_); } else - if (design->modules.count(design->selected_active_module) > 0) + if (design->modules_.count(design->selected_active_module) > 0) { - RTLIL::Module *module = design->modules.at(design->selected_active_module); + RTLIL::Module *module = design->modules_.at(design->selected_active_module); counter += log_matches("wires", pattern, module->wires_); counter += log_matches("memories", pattern, module->memories); counter += log_matches("cells", pattern, module->cells_); diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index ea5221f6..029c0ec7 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -98,7 +98,7 @@ struct SetattrPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; @@ -164,7 +164,7 @@ struct SetparamPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod : design->modules) + for (auto &mod : design->modules_) { RTLIL::Module *module = mod.second; diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index e7779415..c72e64b8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -115,7 +115,7 @@ struct SetundefPass : public Pass { if (!got_value) log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (!design->selected(module)) diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 18af8dfc..7ab1daf0 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -506,7 +506,7 @@ struct ShowWorker design->optimize(); page_counter = 0; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { module = mod_it.second; if (!design->selected_module(module->name)) @@ -692,7 +692,7 @@ struct ShowPass : public Pass { if (format != "ps") { int modcount = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index dcd2f819..5fce2d6c 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -327,7 +327,7 @@ struct SplicePass : public Pass { log_header("Executing SPLICE pass (creating cells for signal splicing).\n"); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index 0998a162..6b1dbe13 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -117,7 +117,7 @@ struct SplitnetsPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (!design->selected(module)) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 153226ab..fabc80ec 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -166,16 +166,16 @@ struct StatPass : public Pass { for (argidx = 1; argidx < args.size(); argidx++) { if (args[argidx] == "-top" && argidx+1 < args.size()) { - if (design->modules.count(RTLIL::escape_id(args[argidx+1])) == 0) + if (design->modules_.count(RTLIL::escape_id(args[argidx+1])) == 0) log_cmd_error("Can't find module %s.\n", args[argidx+1].c_str()); - top_mod = design->modules.at(RTLIL::escape_id(args[++argidx])); + top_mod = design->modules_.at(RTLIL::escape_id(args[++argidx])); continue; } break; } extra_args(args, argidx, design); - for (auto &it : design->modules) + for (auto &it : design->modules_) { if (!design->selected_module(it.first)) continue; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index e1528f31..a619cf57 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -148,7 +148,7 @@ struct FsmDetectPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 40ec55c1..f107366d 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -258,7 +258,7 @@ struct FsmExpandPass : public Pass { log_header("Executing FSM_EXPAND pass (merging auxiliary logic into FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index 129e7f9a..f84f372a 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -174,7 +174,7 @@ struct FsmExportPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 64b01064..99352b10 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -330,7 +330,7 @@ struct FsmExtractPass : public Pass { ct.setup_stdcells(); ct.setup_stdcells_mem(); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index 4526939c..45d68a90 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -43,7 +43,7 @@ struct FsmInfoPass : public Pass { log_header("Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index f6ef12a7..8b9ad6be 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -309,7 +309,7 @@ struct FsmMapPass : public Pass { log_header("Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 165b0974..9d9156ae 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -288,7 +288,7 @@ struct FsmOptPass : public Pass { log_header("Executing FSM_OPT pass (simple optimizations of FSMs).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second)) diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index 1b2eeb23..40fed130 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -144,7 +144,7 @@ struct FsmRecodePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 550ec39f..8aec25eb 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -37,11 +37,11 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell { std::set<std::string> found_celltypes; - for (auto i1 : design->modules) + for (auto i1 : design->modules_) for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; - if (cell->type[0] == '$' || design->modules.count(cell->type) > 0) + if (cell->type[0] == '$' || design->modules_.count(cell->type) > 0) continue; for (auto &pattern : celltypes) if (!fnmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str(), FNM_NOESCAPE)) @@ -55,7 +55,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell std::map<std::string, int> portwidths; log("Generate module for cell type %s:\n", celltype.c_str()); - for (auto i1 : design->modules) + for (auto i1 : design->modules_) for (auto i2 : i1.second->cells_) if (i2.second->type == celltype) { for (auto &conn : i2.second->connections()) { @@ -115,7 +115,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell RTLIL::Module *mod = new RTLIL::Module; mod->name = celltype; mod->attributes["\\blackbox"] = RTLIL::Const(1); - design->modules[mod->name] = mod; + design->modules_[mod->name] = mod; for (auto &decl : ports) { RTLIL::Wire *wire = mod->addWire(decl.portname, portwidths.at(decl.portname)); @@ -151,11 +151,11 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla cell->type = cell->type.substr(pos_type + 1); } - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) { - if (design->modules.count("$abstract" + cell->type)) + if (design->modules_.count("$abstract" + cell->type)) { - cell->type = design->modules.at("$abstract" + cell->type)->derive(design, cell->parameters); + cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; continue; @@ -189,7 +189,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla continue; loaded_module: - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) log_error("File `%s' from libdir does not declare module `%s'.\n", filename.c_str(), cell->type.c_str()); did_something = true; } @@ -197,10 +197,10 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla if (cell->parameters.size() == 0) continue; - if (design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) + if (design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) continue; - RTLIL::Module *mod = design->modules[cell->type]; + RTLIL::Module *mod = design->modules_[cell->type]; cell->type = mod->derive(design, cell->parameters); cell->parameters.clear(); did_something = true; @@ -211,10 +211,10 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla RTLIL::Cell *cell = it.first; int idx = it.second.first, num = it.second.second; - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) log_error("Array cell `%s.%s' of unkown type `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); - RTLIL::Module *mod = design->modules[cell->type]; + RTLIL::Module *mod = design->modules_[cell->type]; for (auto &conn : cell->connections_) { int conn_size = conn.second.size(); @@ -253,8 +253,8 @@ static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &us used.insert(mod); for (auto &it : mod->cells_) { - if (design->modules.count(it.second->type) > 0) - hierarchy_worker(design, used, design->modules[it.second->type], indent+4); + if (design->modules_.count(it.second->type) > 0) + hierarchy_worker(design, used, design->modules_[it.second->type], indent+4); } } @@ -264,7 +264,7 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, hierarchy_worker(design, used, top, 0); std::vector<RTLIL::Module*> del_modules; - for (auto &it : design->modules) + for (auto &it : design->modules_) if (used.count(it.second) == 0) del_modules.push_back(it.second); @@ -274,7 +274,7 @@ static void hierarchy(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib, if (!purge_lib && mod->get_bool_attribute("\\blackbox")) continue; log("Removing unused module `%s'.\n", mod->name.c_str()); - design->modules.erase(mod->name); + design->modules_.erase(mod->name); delete mod; } @@ -412,11 +412,11 @@ struct HierarchyPass : public Pass { if (args[argidx] == "-top") { if (++argidx >= args.size()) log_cmd_error("Option -top requires an additional argument!\n"); - top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL; - if (top_mod == NULL && design->modules.count("$abstract" + RTLIL::escape_id(args[argidx]))) { + top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL; + if (top_mod == NULL && design->modules_.count("$abstract" + RTLIL::escape_id(args[argidx]))) { std::map<RTLIL::IdString, RTLIL::Const> empty_parameters; - design->modules.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters); - top_mod = design->modules.count(RTLIL::escape_id(args[argidx])) ? design->modules.at(RTLIL::escape_id(args[argidx])) : NULL; + design->modules_.at("$abstract" + RTLIL::escape_id(args[argidx]))->derive(design, empty_parameters); + top_mod = design->modules_.count(RTLIL::escape_id(args[argidx])) ? design->modules_.at(RTLIL::escape_id(args[argidx])) : NULL; } if (top_mod == NULL) log_cmd_error("Module `%s' not found!\n", args[argidx].c_str()); @@ -434,7 +434,7 @@ struct HierarchyPass : public Pass { log_push(); if (top_mod == NULL) - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_mod = mod_it.second; @@ -446,13 +446,13 @@ struct HierarchyPass : public Pass { while (did_something) { did_something = false; std::vector<std::string> modnames; - modnames.reserve(design->modules.size()); - for (auto &mod_it : design->modules) + modnames.reserve(design->modules_.size()); + for (auto &mod_it : design->modules_) modnames.push_back(mod_it.first); for (auto &modname : modnames) { - if (design->modules.count(modname) == 0) + if (design->modules_.count(modname) == 0) continue; - if (expand_module(design, design->modules[modname], flag_check, libdirs)) + if (expand_module(design, design->modules_[modname], flag_check, libdirs)) did_something = true; } if (did_something) @@ -465,7 +465,7 @@ struct HierarchyPass : public Pass { } if (top_mod != NULL) { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second == top_mod) mod_it.second->attributes["\\top"] = RTLIL::Const(1); else @@ -478,14 +478,14 @@ struct HierarchyPass : public Pass { std::map<std::pair<RTLIL::Module*,int>, RTLIL::IdString> pos_map; std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) for (auto &cell_it : mod_it.second->cells_) { RTLIL::Cell *cell = cell_it.second; - if (design->modules.count(cell->type) == 0) + if (design->modules_.count(cell->type) == 0) continue; for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { - pos_mods.insert(design->modules.at(cell->type)); + pos_mods.insert(design->modules_.at(cell->type)); pos_work.push_back(std::pair<RTLIL::Module*,RTLIL::Cell*>(mod_it.second, cell)); break; } @@ -507,7 +507,7 @@ struct HierarchyPass : public Pass { for (auto &conn : cell->connections()) if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') { int id = atoi(conn.first.c_str()+1); - std::pair<RTLIL::Module*,int> key(design->modules.at(cell->type), id); + std::pair<RTLIL::Module*,int> key(design->modules_.at(cell->type), id); if (pos_map.count(key) == 0) { log(" Failed to map positional argument %d of cell %s.%s (%s).\n", id, RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 37410275..d32b5e1d 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -105,7 +105,7 @@ struct SubmodWorker RTLIL::Module *new_mod = new RTLIL::Module; new_mod->name = submod.full_name; - design->modules[new_mod->name] = new_mod; + design->modules_[new_mod->name] = new_mod; int port_counter = 1, auto_name_counter = 1; std::set<std::string> all_wire_names; @@ -229,7 +229,7 @@ struct SubmodWorker if (submodules.count(submod_str) == 0) { submodules[submod_str].name = submod_str; submodules[submod_str].full_name = module->name + "_" + submod_str; - while (design->modules.count(submodules[submod_str].full_name) != 0 || + while (design->modules_.count(submodules[submod_str].full_name) != 0 || module->count_id(submodules[submod_str].full_name) != 0) submodules[submod_str].full_name += "_"; } @@ -312,12 +312,12 @@ struct SubmodPass : public Pass { while (did_something) { did_something = false; std::vector<std::string> queued_modules; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first)) queued_modules.push_back(mod_it.first); for (auto &modname : queued_modules) - if (design->modules.count(modname) != 0) { - SubmodWorker worker(design, design->modules[modname]); + if (design->modules_.count(modname) != 0) { + SubmodWorker worker(design, design->modules_[modname]); handled_modules.insert(modname); did_something = true; } @@ -328,7 +328,7 @@ struct SubmodPass : public Pass { else { RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_module(mod_it.first)) continue; if (module != NULL) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index d5995ee0..d2803ae7 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -200,7 +200,7 @@ struct MemoryCollectPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index bb8b052d..9a1e9679 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -212,7 +212,7 @@ struct MemoryDffPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second, flag_wr_only); } diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4bb0c8cc..53394b19 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -317,7 +317,7 @@ struct MemoryMapPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index b25cf73a..e61661a2 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -734,7 +734,7 @@ struct MemorySharePass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_SHARE pass (consolidating $memrc/$memwr cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) MemoryShareWorker(design, mod_it.second); } diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index 48b83f5f..d2b9c0ee 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -102,7 +102,7 @@ struct MemoryUnpackPass : public Pass { virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { log_header("Executing MEMORY_UNPACK pass (generating $memrd/$memwr cells form $mem cells).\n"); extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) handle_module(design, mod_it.second); } diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 4cc5fc89..c219bc04 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -338,7 +338,7 @@ struct OptCleanPass : public Pass { ct_reg.setup_internals_mem(); ct_reg.setup_stdcells_mem(); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_whole_module(mod_it.first)) { if (design->selected(mod_it.second)) log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name)); @@ -402,7 +402,7 @@ struct CleanPass : public Pass { count_rm_cells = 0; count_rm_wires = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (design->selected_whole_module(mod_it.first) && mod_it.second->processes.size() == 0) do { OPT_DID_SOMETHING = false; diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 39e2254e..bfd0161b 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -939,7 +939,7 @@ struct OptConstPass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (undriven) replace_undriven(design, mod_it.second); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 1d4916b5..82cc78be 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -423,7 +423,7 @@ struct OptMuxtreePass : public Pass { extra_args(args, 1, design); int total_count = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected_whole_module(mod_it.first)) { if (design->selected(mod_it.second)) log("Skipping module %s as it is only partially selected.\n", id2cstr(mod_it.second->name)); diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index d7de7235..b2b7cc8b 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -367,7 +367,7 @@ struct OptReducePass : public Pass { extra_args(args, argidx, design); int total_count = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; OptReduceWorker worker(design, mod_it.second, do_fine); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index 14b734d7..b01778b5 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -166,7 +166,7 @@ struct OptRmdffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index 304ba9f8..45130229 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -315,7 +315,7 @@ struct OptSharePass : public Pass { extra_args(args, argidx, design); int total_count = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; OptShareWorker worker(design, mod_it.second, mode_nomux); diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 63d04d35..e8439477 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -236,7 +236,7 @@ struct ProcArstPass : public Pass { extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { SigMap assign_map(mod_it.second); for (auto &proc_it : mod_it.second->processes) { diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 682515c5..678d620b 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -149,7 +149,7 @@ struct ProcCleanPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { std::vector<std::string> delme; if (!design->selected(mod_it.second)) continue; diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index cfd2eb7a..7bd909a6 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -371,7 +371,7 @@ struct ProcDffPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { ConstEval ce(mod_it.second); for (auto &proc_it : mod_it.second->processes) diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 5976c216..3607905f 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -101,7 +101,7 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 67113a68..bcbee6cf 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -276,7 +276,7 @@ struct ProcMuxPass : public Pass { extra_args(args, 1, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) for (auto &proc_it : mod_it.second->processes) if (design->selected(mod_it.second, proc_it.second)) diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index d5fbef0d..e7e4bbc5 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -79,7 +79,7 @@ struct ProcRmdeadPass : public Pass { extra_args(args, 1, design); int total_counter = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; for (auto &proc_it : mod_it.second->processes) { diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index 45423326..8a2dd929 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -306,10 +306,10 @@ struct VlogHammerReporter { for (auto name : split(module_list, ",")) { RTLIL::IdString esc_name = RTLIL::escape_id(module_prefix + name); - if (design->modules.count(esc_name) == 0) + if (design->modules_.count(esc_name) == 0) log_error("Can't find module %s in current design!\n", name.c_str()); log("Using module %s (%s).\n", esc_name.c_str(), name.c_str()); - modules.push_back(design->modules.at(esc_name)); + modules.push_back(design->modules_.at(esc_name)); module_names.push_back(name); } @@ -416,11 +416,11 @@ struct EvalPass : public Pass { /* this should only be used for regression testing of ConstEval -- see vloghammer */ std::string mod1_name = RTLIL::escape_id(args[++argidx]); std::string mod2_name = RTLIL::escape_id(args[++argidx]); - if (design->modules.count(mod1_name) == 0) + if (design->modules_.count(mod1_name) == 0) log_error("Can't find module `%s'!\n", mod1_name.c_str()); - if (design->modules.count(mod2_name) == 0) + if (design->modules_.count(mod2_name) == 0) log_error("Can't find module `%s'!\n", mod2_name.c_str()); - BruteForceEquivChecker checker(design->modules.at(mod1_name), design->modules.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); + BruteForceEquivChecker checker(design->modules_.at(mod1_name), design->modules_.at(mod2_name), args[argidx-2] == "-brute_force_equiv_checker_x"); if (checker.errors > 0) log_cmd_error("Modules are not equivialent!\n"); log("Verified %s = %s (using brute-force check on %d cases).\n", @@ -442,7 +442,7 @@ struct EvalPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the EVAL pass! (selected: %s and %s)\n", diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index 24b812bb..f2b89b00 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -50,7 +50,7 @@ static bool consider_cell(RTLIL::Design *design, std::set<std::string> &dff_cell { if (cell->name[0] == '$' || dff_cells.count(cell->name)) return false; - if (cell->type.at(0) == '\\' && !design->modules.count(cell->type)) + if (cell->type.at(0) == '\\' && !design->modules_.count(cell->type)) return false; return true; } @@ -302,7 +302,7 @@ struct ExposePass : public Pass { RTLIL::Module *first_module = NULL; std::set<std::string> shared_dff_wires; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; @@ -352,7 +352,7 @@ struct ExposePass : public Pass { { RTLIL::Module *first_module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; @@ -434,7 +434,7 @@ struct ExposePass : public Pass { } } - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; @@ -583,9 +583,9 @@ struct ExposePass : public Pass { RTLIL::Cell *cell = it.second; - if (design->modules.count(cell->type)) + if (design->modules_.count(cell->type)) { - RTLIL::Module *mod = design->modules.at(cell->type); + RTLIL::Module *mod = design->modules_.at(cell->type); for (auto &it : mod->wires_) { diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index f8d5cf6c..ad304c72 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -817,7 +817,7 @@ struct FreducePass : public Pass { extra_args(args, argidx, design); int bitcount = 0; - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { RTLIL::Module *module = mod_it.second; if (design->selected(module)) bitcount += FreduceWorker(design, module).run(); diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 248f934c..0f00e71a 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -63,15 +63,15 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, std::string gate_name = RTLIL::escape_id(args[argidx++]); std::string miter_name = RTLIL::escape_id(args[argidx++]); - if (design->modules.count(gold_name) == 0) + if (design->modules_.count(gold_name) == 0) log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); - if (design->modules.count(gate_name) == 0) + if (design->modules_.count(gate_name) == 0) log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); - if (design->modules.count(miter_name) != 0) + if (design->modules_.count(miter_name) != 0) log_cmd_error("There is already a module %s!\n", gate_name.c_str()); - RTLIL::Module *gold_module = design->modules.at(gold_name); - RTLIL::Module *gate_module = design->modules.at(gate_name); + RTLIL::Module *gold_module = design->modules_.at(gold_name); + RTLIL::Module *gate_module = design->modules_.at(gate_name); for (auto &it : gold_module->wires_) { RTLIL::Wire *w1 = it.second, *w2; @@ -113,7 +113,7 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL::Module *miter_module = new RTLIL::Module; miter_module->name = miter_name; - design->modules[miter_name] = miter_module; + design->modules_[miter_name] = miter_module; RTLIL::Cell *gold_cell = miter_module->addCell("\\gold", gold_name); RTLIL::Cell *gate_cell = miter_module->addCell("\\gate", gate_name); diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 3e1c7222..dce31206 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -1141,7 +1141,7 @@ struct SatPass : public Pass { extra_args(args, argidx, design); RTLIL::Module *module = NULL; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) { if (module) log_cmd_error("Only one module must be selected for the SAT pass! (selected: %s and %s)\n", diff --git a/passes/sat/share.cc b/passes/sat/share.cc index facacf19..671a631d 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -961,7 +961,7 @@ struct SharePass : public Pass { } extra_args(args, argidx, design); - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (design->selected(mod_it.second)) ShareWorker(config, design, mod_it.second); } diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index 01284656..ffe24118 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -524,7 +524,7 @@ struct DfflibmapPass : public Pass { log(" final dff cell mappings:\n"); logmap_all(); - for (auto &it : design->modules) + for (auto &it : design->modules_) if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox")) dfflibmap(design, it.second); diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index b66a11b8..8587f53b 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -604,9 +604,9 @@ struct ExtractPass : public Pass { delete map; log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1); } - for (auto &it : saved_designs.at(filename.substr(1))->modules) - if (!map->modules.count(it.first)) - map->modules[it.first] = it.second->clone(); + for (auto &it : saved_designs.at(filename.substr(1))->modules_) + if (!map->modules_.count(it.first)) + map->modules_[it.first] = it.second->clone(); } else { @@ -632,7 +632,7 @@ struct ExtractPass : public Pass { log_header("Creating graphs for SubCircuit library.\n"); if (!mine_mode) - for (auto &mod_it : map->modules) { + for (auto &mod_it : map->modules_) { SubCircuit::Graph mod_graph; std::string graph_name = "needle_" + RTLIL::unescape_id(mod_it.first); log("Creating needle graph %s.\n", graph_name.c_str()); @@ -643,7 +643,7 @@ struct ExtractPass : public Pass { } } - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { SubCircuit::Graph mod_graph; std::string graph_name = "haystack_" + RTLIL::unescape_id(mod_it.first); log("Creating haystack graph %s.\n", graph_name.c_str()); @@ -725,7 +725,7 @@ struct ExtractPass : public Pass { RTLIL::Module *newMod = new RTLIL::Module; newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits); - map->modules[newMod->name] = newMod; + map->modules_[newMod->name] = newMod; int portCounter = 1; for (auto wire : wires) { diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc index 30977787..a3261dcc 100644 --- a/passes/techmap/hilomap.cc +++ b/passes/techmap/hilomap.cc @@ -104,7 +104,7 @@ struct HilomapPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules) + for (auto &it : design->modules_) { module = it.second; diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 6f7427f0..10627cd1 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -111,7 +111,7 @@ struct IopadmapPass : public Pass { } extra_args(args, argidx, design); - for (auto &it : design->modules) + for (auto &it : design->modules_) { RTLIL::Module *module = it.second; diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 8c7f6423..6def1008 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -435,7 +435,7 @@ struct SimplemapPass : public Pass { std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers; simplemap_get_mappers(mappers); - for (auto &mod_it : design->modules) { + for (auto &mod_it : design->modules_) { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> delete_cells; diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 86d9e73a..32e18e08 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -243,7 +243,7 @@ struct TechmapWorker for (auto &tpl_name : celltypeMap.at(cell->type)) { std::string derived_name = tpl_name; - RTLIL::Module *tpl = map->modules[tpl_name]; + RTLIL::Module *tpl = map->modules_[tpl_name]; std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters; if (tpl->get_bool_attribute("\\blackbox")) @@ -334,7 +334,7 @@ struct TechmapWorker } else { if (cell->parameters.size() != 0) { derived_name = tpl->derive(map, parameters); - tpl = map->modules[derived_name]; + tpl = map->modules_[derived_name]; log_continue = true; } techmap_cache[key] = tpl; @@ -592,15 +592,15 @@ struct TechmapPass : public Pass { } std::map<RTLIL::IdString, RTLIL::Module*> modules_new; - for (auto &it : map->modules) { + for (auto &it : map->modules_) { if (it.first.substr(0, 2) == "\\$") it.second->name = it.first.substr(1); modules_new[it.second->name] = it.second; } - map->modules.swap(modules_new); + map->modules_.swap(modules_new); std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap; - for (auto &it : map->modules) { + for (auto &it : map->modules_) { if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) { char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str()); for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n")) @@ -614,7 +614,7 @@ struct TechmapPass : public Pass { std::set<RTLIL::Cell*> handled_cells; while (did_something) { did_something = false; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false)) did_something = true; if (did_something) @@ -653,12 +653,12 @@ struct FlattenPass : public Pass { TechmapWorker worker; std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap; - for (auto &it : design->modules) + for (auto &it : design->modules_) celltypeMap[it.first].insert(it.first); RTLIL::Module *top_mod = NULL; if (design->full_selection()) - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second->get_bool_attribute("\\top")) top_mod = mod_it.second; @@ -670,7 +670,7 @@ struct FlattenPass : public Pass { if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true)) did_something = true; } else { - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true)) did_something = true; } @@ -680,14 +680,14 @@ struct FlattenPass : public Pass { if (top_mod != NULL) { std::map<RTLIL::IdString, RTLIL::Module*> new_modules; - for (auto &mod_it : design->modules) + for (auto &mod_it : design->modules_) if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) { new_modules[mod_it.first] = mod_it.second; } else { log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first)); delete mod_it.second; } - design->modules.swap(new_modules); + design->modules_.swap(new_modules); } log_pop(); |