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-rw-r--r--passes/cmds/delete.cc2
-rw-r--r--passes/cmds/setundef.cc2
-rw-r--r--passes/cmds/show.cc4
-rw-r--r--passes/cmds/splitnets.cc2
-rw-r--r--passes/fsm/fsm_extract.cc4
-rw-r--r--passes/hierarchy/submod.cc2
-rw-r--r--passes/memory/memory_dff.cc2
-rw-r--r--passes/opt/opt_const.cc9
-rw-r--r--passes/proc/proc_arst.cc2
-rw-r--r--passes/sat/eval.cc4
-rw-r--r--passes/techmap/extract.cc2
-rw-r--r--passes/techmap/hilomap.cc2
-rw-r--r--passes/techmap/techmap.cc2
13 files changed, 17 insertions, 22 deletions
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index c5aa196c..f433c4b4 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -28,7 +28,7 @@ struct DeleteWireWorker
void operator()(RTLIL::SigSpec &sig) {
sig.optimize();
- for (auto &c : sig.chunks())
+ for (auto &c : sig.chunks_rw())
if (c.wire != NULL && delete_wires_p->count(c.wire->name)) {
c.wire = module->addWire(NEW_ID, c.width);
c.offset = 0;
diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc
index 7558a4e9..619930b3 100644
--- a/passes/cmds/setundef.cc
+++ b/passes/cmds/setundef.cc
@@ -48,7 +48,7 @@ struct SetundefWorker
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.chunks())
+ for (auto &c : sig.chunks_rw())
if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1)
c.data.bits.at(0) = next_bit();
sig.optimize();
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index fde96d53..37fe4404 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -179,7 +179,7 @@ struct ShowWorker
}
if (sig.chunks().size() == 1) {
- RTLIL::SigChunk &c = sig.chunks()[0];
+ const RTLIL::SigChunk &c = sig.chunks()[0];
if (c.wire != NULL && design->selected_member(module->name, c.wire->name)) {
if (!range_check || c.wire->width == c.width)
return stringf("n%d", id2num(c.wire->name));
@@ -203,7 +203,7 @@ struct ShowWorker
int pos = sig.size()-1;
int idx = single_idx_count++;
for (int i = int(sig.chunks().size())-1; i >= 0; i--) {
- RTLIL::SigChunk &c = sig.chunks()[i];
+ const RTLIL::SigChunk &c = sig.chunks()[i];
net = gen_signode_simple(c, false);
assert(!net.empty());
if (driver) {
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 8cc6a515..d71e9727 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -63,7 +63,7 @@ struct SplitnetsWorker
void operator()(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.chunks())
+ for (auto &c : sig.chunks_rw())
if (splitmap.count(c.wire) > 0)
c = splitmap.at(c.wire).at(c.offset);
sig.optimize();
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index 701b09bd..c3bb1933 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -92,7 +92,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
{
if (dont_care.size() > 0) {
sig.expand();
- for (auto &chunk : sig.chunks()) {
+ for (auto &chunk : sig.chunks_rw()) {
assert(chunk.width == 1);
if (dont_care.extract(chunk).size() > 0)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
@@ -104,7 +104,7 @@ static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State no
ce.values_map.apply(sig);
sig.expand();
- for (auto &chunk : sig.chunks()) {
+ for (auto &chunk : sig.chunks_rw()) {
assert(chunk.width == 1);
if (chunk.wire != NULL)
chunk.wire = NULL, chunk.data = RTLIL::Const(noconst_state);
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index fa8043c8..b983a840 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -164,7 +164,7 @@ struct SubmodWorker
for (RTLIL::Cell *cell : submod.cells) {
RTLIL::Cell *new_cell = new RTLIL::Cell(*cell);
for (auto &conn : new_cell->connections)
- for (auto &c : conn.second.chunks())
+ for (auto &c : conn.second.chunks_rw())
if (c.wire != NULL) {
assert(wire_flags.count(c.wire) > 0);
c.wire = wire_flags[c.wire].new_wire;
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index 8bae24cf..dee48597 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -36,7 +36,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI
for (size_t i = 0; i < sig.chunks().size(); i++)
{
- RTLIL::SigChunk &chunk = sig.chunks()[i];
+ RTLIL::SigChunk &chunk = sig.chunks_rw()[i];
if (chunk.wire == NULL)
continue;
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 1a1f0fe4..9b89291b 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -699,10 +699,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
RTLIL::SigSpec a = cell->connections["\\A"]; \
assign_map.apply(a); \
if (a.is_fully_const()) { \
- a.optimize(); \
- if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
- RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, dummy_arg, \
+ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
cell->parameters["\\A_SIGNED"].as_bool(), false, \
cell->parameters["\\Y_WIDTH"].as_int())); \
replace_cell(module, cell, stringf("%s", log_signal(a)), "\\Y", y); \
@@ -715,10 +713,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
RTLIL::SigSpec b = cell->connections["\\B"]; \
assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \
- a.optimize(), b.optimize(); \
- if (a.chunks().empty()) a.chunks().push_back(RTLIL::SigChunk()); \
- if (b.chunks().empty()) b.chunks().push_back(RTLIL::SigChunk()); \
- RTLIL::SigSpec y(RTLIL::const_ ## _t(a.chunks()[0].data, b.chunks()[0].data, \
+ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
cell->parameters["\\A_SIGNED"].as_bool(), \
cell->parameters["\\B_SIGNED"].as_bool(), \
cell->parameters["\\Y_WIDTH"].as_int())); \
diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc
index b5763508..6cb560f5 100644
--- a/passes/proc/proc_arst.cc
+++ b/passes/proc/proc_arst.cc
@@ -168,7 +168,7 @@ restart_proc_arst:
rspec.expand(), rval.expand();
for (int i = 0; i < int(rspec.chunks().size()); i++)
if (rspec.chunks()[i].wire == NULL)
- rval.chunks()[i] = rspec.chunks()[i];
+ rval.chunks_rw()[i] = rspec.chunks()[i];
rspec.optimize(), rval.optimize();
RTLIL::SigSpec last_rval;
for (int count = 0; rval != last_rval; count++) {
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 03a86246..73235e93 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -73,7 +73,7 @@ struct BruteForceEquivChecker
sig1.expand(), sig2.expand();
for (size_t i = 0; i < sig1.chunks().size(); i++)
if (sig1.chunks().at(i) == RTLIL::SigChunk(RTLIL::State::Sx))
- sig2.chunks().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
+ sig2.chunks_rw().at(i) = RTLIL::SigChunk(RTLIL::State::Sx);
sig1.optimize(), sig2.optimize();
}
@@ -299,7 +299,7 @@ struct VlogHammerReporter
log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
for (int i = 0; i < sig.size(); i++)
if (rtl_sig.chunks().at(i).data.bits.at(0) == RTLIL::State::Sx)
- sig.chunks().at(i).data.bits.at(0) = RTLIL::State::Sx;
+ sig.chunks_rw().at(i).data.bits.at(0) = RTLIL::State::Sx;
}
log("++RPT++ %d%s %s %s\n", idx, input_pattern_list.c_str(), sig.as_const().as_string().c_str(), module_name.c_str());
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index a960f2ba..5a729808 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -756,7 +756,7 @@ struct ExtractPass : public Pass {
newCell->parameters = cell->parameters;
for (auto &conn : cell->connections) {
RTLIL::SigSpec sig = sigmap(conn.second);
- for (auto &chunk : sig.chunks())
+ for (auto &chunk : sig.chunks_rw())
if (chunk.wire != NULL)
chunk.wire = newMod->wires.at(chunk.wire->name);
newCell->connections[conn.first] = sig;
diff --git a/passes/techmap/hilomap.cc b/passes/techmap/hilomap.cc
index ac41e47c..53c5d104 100644
--- a/passes/techmap/hilomap.cc
+++ b/passes/techmap/hilomap.cc
@@ -31,7 +31,7 @@ static RTLIL::SigChunk last_hi, last_lo;
void hilomap_worker(RTLIL::SigSpec &sig)
{
sig.expand();
- for (auto &c : sig.chunks()) {
+ for (auto &c : sig.chunks_rw()) {
if (c.wire == NULL && (c.data.bits.at(0) == RTLIL::State::S1) && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi.width == 0) {
last_hi = RTLIL::SigChunk(module->addWire(NEW_ID));
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index d3e7e20f..f3b1a0ef 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -47,7 +47,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
std::string wire_name = sig.chunks()[i].wire->name;
apply_prefix(prefix, wire_name);
assert(module->wires.count(wire_name) > 0);
- sig.chunks()[i].wire = module->wires[wire_name];
+ sig.chunks_rw()[i].wire = module->wires[wire_name];
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-23 19:22:59 +0000