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Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/delete.cc4
-rw-r--r--passes/cmds/splitnets.cc2
-rw-r--r--passes/opt/opt_clean.cc2
-rw-r--r--passes/opt/opt_const.cc2
-rw-r--r--passes/opt/opt_share.cc2
-rw-r--r--passes/opt/share.cc4
6 files changed, 8 insertions, 8 deletions
diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc
index 5bf2a36b..b4362887 100644
--- a/passes/cmds/delete.cc
+++ b/passes/cmds/delete.cc
@@ -91,8 +91,8 @@ struct DeletePass : public Pass {
continue;
}
- pool<RTLIL::Wire*, hash_obj_ops> delete_wires;
- pool<RTLIL::Cell*, hash_obj_ops> delete_cells;
+ pool<RTLIL::Wire*> delete_wires;
+ pool<RTLIL::Cell*> delete_cells;
pool<RTLIL::IdString> delete_procs;
pool<RTLIL::IdString> delete_mems;
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 2523c166..d4e721a5 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -176,7 +176,7 @@ struct SplitnetsPass : public Pass {
module->rewrite_sigspecs(worker);
- pool<RTLIL::Wire*, hash_obj_ops> delete_wires;
+ pool<RTLIL::Wire*> delete_wires;
for (auto &it : worker.splitmap)
delete_wires.insert(it.first);
module->remove(delete_wires);
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index b387e038..b9ff5d30 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -262,7 +262,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
}
- pool<RTLIL::Wire*, hash_obj_ops> del_wires;
+ pool<RTLIL::Wire*> del_wires;
int del_wires_count = 0;
for (auto wire : maybe_del_wires)
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index f78ea6cc..7f800bde 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -199,7 +199,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
- dict<RTLIL::Cell*, std::set<RTLIL::SigBit>, hash_obj_ops> cell_to_inbit;
+ dict<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_inbit;
dict<RTLIL::SigBit, std::set<RTLIL::Cell*>> outbit_to_cell;
for (auto cell : module->cells())
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 91bfd58a..c581b749 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -41,7 +41,7 @@ struct OptShareWorker
CellTypes ct;
int total_count;
#ifdef USE_CELL_HASH_CACHE
- dict<const RTLIL::Cell*, std::string, hash_obj_ops> cell_hash_cache;
+ dict<const RTLIL::Cell*, std::string> cell_hash_cache;
#endif
#ifdef USE_CELL_HASH_CACHE
diff --git a/passes/opt/share.cc b/passes/opt/share.cc
index 41a4a690..0d1a54d9 100644
--- a/passes/opt/share.cc
+++ b/passes/opt/share.cc
@@ -731,7 +731,7 @@ struct ShareWorker
return forbidden_controls_cache.at(cell);
pool<ModWalker::PortBit> pbits;
- pool<RTLIL::Cell*, hash_obj_ops> consumer_cells;
+ pool<RTLIL::Cell*> consumer_cells;
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
@@ -803,7 +803,7 @@ struct ShareWorker
return activation_patterns_cache.at(cell);
const pool<RTLIL::SigBit> &cell_out_bits = modwalker.cell_outputs[cell];
- pool<RTLIL::Cell*, hash_obj_ops> driven_cells, driven_data_muxes;
+ pool<RTLIL::Cell*> driven_cells, driven_data_muxes;
for (auto &bit : cell_out_bits)
{