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Diffstat (limited to 'passes')
-rw-r--r--passes/cmds/select.cc10
-rw-r--r--passes/hierarchy/hierarchy.cc4
2 files changed, 7 insertions, 7 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index af0df07b..8e42fe15 100644
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1142,7 +1142,7 @@ struct SelectPass : public Pass {
if (list_mode || count_mode || !write_file.empty())
{
- #define LOG_OBJECT(...) do { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; } while (0)
+ #define LOG_OBJECT(...) { if (list_mode) log(__VA_ARGS__); if (f != NULL) fprintf(f, __VA_ARGS__); total_count++; }
int total_count = 0;
FILE *f = NULL;
if (!write_file.empty()) {
@@ -1161,16 +1161,16 @@ struct SelectPass : public Pass {
if (sel->selected_module(mod_it.first)) {
for (auto &it : mod_it.second->wires_)
if (sel->selected_member(mod_it.first, it.first))
- LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+ LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first))
for (auto &it : mod_it.second->memories)
if (sel->selected_member(mod_it.first, it.first))
- LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+ LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first))
for (auto &it : mod_it.second->cells_)
if (sel->selected_member(mod_it.first, it.first))
- LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+ LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first))
for (auto &it : mod_it.second->processes)
if (sel->selected_member(mod_it.first, it.first))
- LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
+ LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first))
}
}
if (count_mode)
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 2a7e9634..0ea26eb9 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -174,7 +174,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &dir : libdirs)
{
filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".v";
- if (access(filename.c_str(), F_OK) == 0) {
+ if (check_file_exists(filename)) {
std::vector<std::string> args;
args.push_back(filename);
Frontend::frontend_call(design, NULL, filename, "verilog");
@@ -182,7 +182,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
}
filename = dir + "/" + RTLIL::unescape_id(cell->type) + ".il";
- if (access(filename.c_str(), F_OK) == 0) {
+ if (check_file_exists(filename)) {
std::vector<std::string> args;
args.push_back(filename);
Frontend::frontend_call(design, NULL, filename, "ilang");