diff options
Diffstat (limited to 'passes')
46 files changed, 117 insertions, 117 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 184f143a..7ba9424e 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -462,7 +462,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int best_dff_counter = 0; std::map<std::pair<bool, RTLIL::SigSpec>, int> dff_counters; - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (cell->type != "$_DFF_N_" && cell->type != "$_DFF_P_") @@ -488,8 +488,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std mark_port(clk_sig); std::vector<RTLIL::Cell*> cells; - cells.reserve(module->cells.size()); - for (auto &it : module->cells) + cells.reserve(module->cells_.size()); + for (auto &it : module->cells_) if (design->selected(current_module, it.second)) cells.push_back(it.second); for (auto c : cells) @@ -500,7 +500,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std mark_port(RTLIL::SigSpec(wire_it.second)); } - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) for (auto &port_it : cell_it.second->connections()) mark_port(port_it.second); @@ -696,7 +696,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std std::map<std::string, int> cell_stats; if (builtin_lib) { - for (auto &it : mapped_mod->cells) { + for (auto &it : mapped_mod->cells_) { RTLIL::Cell *c = it.second; cell_stats[RTLIL::unescape_id(c->type)]++; if (c->type == "\\ZERO" || c->type == "\\ONE") { @@ -751,7 +751,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std } else { - for (auto &it : mapped_mod->cells) + for (auto &it : mapped_mod->cells_) { RTLIL::Cell *c = it.second; cell_stats[RTLIL::unescape_id(c->type)]++; diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index e97bf8fc..49aa7c98 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -62,7 +62,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n if (!flag_global) return; - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (design->modules.count(it.second->type) == 0) continue; diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 99a28d4a..6494ea6f 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -29,7 +29,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap & RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size()); - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &port : it.second->connections_) if (ct.cell_output(it.second->type, port.first)) sigmap(port.second).replace(sig, dummy_wire, &port.second); @@ -169,14 +169,14 @@ struct ConnectPass : public Pass { if (flag_nounset) log_cmd_error("Cant use -port together with -nounset.\n"); - if (module->cells.count(RTLIL::escape_id(port_cell)) == 0) + if (module->cells_.count(RTLIL::escape_id(port_cell)) == 0) log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); - module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); + module->cells_.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig)); } else log_cmd_error("Expected -set, -unset, or -port.\n"); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index 9faeffaf..cc8147c5 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -67,7 +67,7 @@ struct ConnwrappersWorker std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map; SigMap sigmap(module); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; @@ -102,7 +102,7 @@ struct ConnwrappersWorker } } - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/cmds/delete.cc b/passes/cmds/delete.cc index 460dd966..2c2c370d 100644 --- a/passes/cmds/delete.cc +++ b/passes/cmds/delete.cc @@ -103,7 +103,7 @@ struct DeletePass : public Pass { if (design->selected(module, it.second)) delete_mems.insert(it.first); - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second)) delete_cells.insert(it.second); if ((it.second->type == "$memrd" || it.second->type == "$memwr") && diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index e163e724..c8b8160f 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -36,7 +36,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: return; } - for (auto &it : module->cells) + for (auto &it : module->cells_) if (it.first == from_name) { log("Renaming cell %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module)); module->rename(it.second, to_name); @@ -114,13 +114,13 @@ struct RenamePass : public Pass { module->wires_.swap(new_wires); std::map<RTLIL::IdString, RTLIL::Cell*> new_cells; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (it.first[0] == '$' && design->selected(module, it.second)) do it.second->name = stringf("\\_%d_", counter++); while (module->count_id(it.second->name) > 0); new_cells[it.second->name] = it.second; } - module->cells.swap(new_cells); + module->cells_.swap(new_cells); } } else @@ -144,13 +144,13 @@ struct RenamePass : public Pass { module->wires_.swap(new_wires); std::map<RTLIL::IdString, RTLIL::Cell*> new_cells; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second)) if (it.first[0] == '\\') it.second->name = NEW_ID; new_cells[it.second->name] = it.second; } - module->cells.swap(new_cells); + module->cells_.swap(new_cells); } } else diff --git a/passes/cmds/scatter.cc b/passes/cmds/scatter.cc index 0b95fe02..a1c12f1e 100644 --- a/passes/cmds/scatter.cc +++ b/passes/cmds/scatter.cc @@ -48,7 +48,7 @@ struct ScatterPass : public Pass { if (!design->selected(mod_it.second)) continue; - for (auto &c : mod_it.second->cells) + for (auto &c : mod_it.second->cells_) for (auto &p : c.second->connections_) { RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size()); diff --git a/passes/cmds/scc.cc b/passes/cmds/scc.cc index 7e2b2fc9..c9504341 100644 --- a/passes/cmds/scc.cc +++ b/passes/cmds/scc.cc @@ -118,7 +118,7 @@ struct SccWorker if (design->selected(module, it.second)) selectedSignals.add(sigmap(RTLIL::SigSpec(it.second))); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 0cabdc06..306b7a5b 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -167,7 +167,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs) for (auto &it : mod->memories) if (!lhs.selected_member(mod_it.first, it.first)) new_sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (!lhs.selected_member(mod_it.first, it.first)) new_sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) @@ -185,7 +185,7 @@ static void select_op_submod(RTLIL::Design *design, RTLIL::Selection &lhs) { if (lhs.selected_whole_module(mod_it.first)) { - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) { if (design->modules.count(cell_it.second->type) == 0) continue; @@ -282,7 +282,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R lhs.selected_members[mod->name].insert(it.first); for (auto &it : mod->memories) lhs.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) lhs.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) lhs.selected_members[mod->name].insert(it.first); @@ -395,7 +395,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v } } - for (auto &cell : mod->cells) + for (auto &cell : mod->cells_) for (auto &conn : cell.second->connections()) { char last_mode = '-'; @@ -742,12 +742,12 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "c:") { - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "t:") { - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_ids(it.second->type, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else @@ -763,7 +763,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) for (auto &it : mod->memories) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_attr(it.second->attributes, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) @@ -771,7 +771,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) sel.selected_members[mod->name].insert(it.first); } else if (arg_memb.substr(0, 2) == "r:") { - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_attr(it.second->parameters, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else { @@ -783,7 +783,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg) for (auto &it : mod->memories) if (match_ids(it.first, arg_memb)) sel.selected_members[mod->name].insert(it.first); - for (auto &it : mod->cells) + for (auto &it : mod->cells_) if (match_ids(it.first, arg_memb)) sel.selected_members[mod->name].insert(it.first); for (auto &it : mod->processes) @@ -1158,7 +1158,7 @@ struct SelectPass : public Pass { for (auto &it : mod_it.second->memories) if (sel->selected_member(mod_it.first, it.first)) LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); - for (auto &it : mod_it.second->cells) + for (auto &it : mod_it.second->cells_) if (sel->selected_member(mod_it.first, it.first)) LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first)); for (auto &it : mod_it.second->processes) @@ -1225,7 +1225,7 @@ struct SelectPass : public Pass { for (auto &it : mod_it.second->memories) if (sel->selected_member(mod_it.first, it.first)) total_count++; - for (auto &it : mod_it.second->cells) + for (auto &it : mod_it.second->cells_) if (sel->selected_member(mod_it.first, it.first)) total_count++; for (auto &it : mod_it.second->processes) @@ -1303,8 +1303,8 @@ struct CdPass : public Pass { RTLIL::Module *module = NULL; if (design->modules.count(design->selected_active_module) > 0) module = design->modules.at(design->selected_active_module); - if (module != NULL && module->cells.count(modname) > 0) - modname = module->cells.at(modname)->type; + if (module != NULL && module->cells_.count(modname) > 0) + modname = module->cells_.at(modname)->type; } if (design->modules.count(modname) > 0) { @@ -1376,7 +1376,7 @@ struct LsPass : public Pass { RTLIL::Module *module = design->modules.at(design->selected_active_module); counter += log_matches("wires", pattern, module->wires_); counter += log_matches("memories", pattern, module->memories); - counter += log_matches("cells", pattern, module->cells); + counter += log_matches("cells", pattern, module->cells_); counter += log_matches("processes", pattern, module->processes); } diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index 0b4f2a8a..ea5221f6 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -119,7 +119,7 @@ struct SetattrPass : public Pass { if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second)) do_setunset(it.second->attributes, setunset_list); @@ -171,7 +171,7 @@ struct SetparamPass : public Pass { if (!design->selected(module)) continue; - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second)) do_setunset(it.second->parameters, setunset_list); } diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 82dc1d99..e7779415 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -134,7 +134,7 @@ struct SetundefPass : public Pass { undriven_signals.add(sigmap(it.second)); CellTypes ct(design); - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) undriven_signals.del(sigmap(conn.second)); diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index 1feb90af..18af8dfc 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -337,7 +337,7 @@ struct ShowWorker fprintf(f, "}\n"); } - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (!design->selected_member(module->name, it.first)) continue; @@ -516,7 +516,7 @@ struct ShowWorker log("Skipping blackbox module %s.\n", id2cstr(module->name)); continue; } else - if (module->cells.empty() && module->connections().empty() && module->processes.empty()) { + if (module->cells_.empty() && module->connections().empty() && module->processes.empty()) { log("Skipping empty module %s.\n", id2cstr(module->name)); continue; } else @@ -695,7 +695,7 @@ struct ShowPass : public Pass { for (auto &mod_it : design->modules) { if (mod_it.second->get_bool_attribute("\\blackbox")) continue; - if (mod_it.second->cells.empty() && mod_it.second->connections().empty()) + if (mod_it.second->cells_.empty() && mod_it.second->connections().empty()) continue; if (design->selected_module(mod_it.first)) modcount++; diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc index 691d972c..dcd2f819 100644 --- a/passes/cmds/splice.cc +++ b/passes/cmds/splice.cc @@ -158,7 +158,7 @@ struct SpliceWorker driven_bits.push_back(RTLIL::State::Sm); } - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &conn : it.second->connections()) if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) { RTLIL::SigSpec sig = sigmap(conn.second); @@ -179,7 +179,7 @@ struct SpliceWorker if (design->selected(module, it.second)) selected_bits.add(sigmap(it.second)); - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (!sel_by_wire && !design->selected(module, it.second)) continue; for (auto &conn : it.second->connections_) diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc index accb178b..0998a162 100644 --- a/passes/cmds/splitnets.cc +++ b/passes/cmds/splitnets.cc @@ -131,7 +131,7 @@ struct SplitnetsPass : public Pass { std::map<RTLIL::Wire*, std::set<int>> split_wires_at; - for (auto &c : module->cells) + for (auto &c : module->cells_) for (auto &p : c.second->connections()) { if (!ct.cell_known(c.second->type)) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index fabf1a73..153226ab 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -90,7 +90,7 @@ namespace num_memory_bits += it.second->width * it.second->size; } - for (auto &it : mod->cells) { + for (auto &it : mod->cells_) { if (!design->selected(mod, it.second)) continue; num_cells++; diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index cb420f90..e1528f31 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -159,7 +159,7 @@ struct FsmDetectPass : public Pass { sig2driver.clear(); sig2user.clear(); sig_at_port.clear(); - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index 186ea2fd..40ec55c1 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -205,7 +205,7 @@ struct FsmExpand assign_map.set(module); ct.setup_internals(); - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *c = cell_it.second; if (ct.cell_known(c->type) && design->selected(mod, c)) for (auto &p : c->connections()) { @@ -262,7 +262,7 @@ struct FsmExpandPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_cells.push_back(cell_it.second); for (auto c : fsm_cells) { diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc index cc328ce3..129e7f9a 100644 --- a/passes/fsm/fsm_export.cc +++ b/passes/fsm/fsm_export.cc @@ -176,7 +176,7 @@ struct FsmExportPass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { attr_it = cell_it.second->attributes.find("\\fsm_export"); if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) { diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 85ff4af2..64b01064 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -53,7 +53,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL std::set<sig2driver_entry_t> cellport_list; sig2driver.find(sig, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != "$mux" && cell->type != "$pmux" && cell->type != "$safe_pmux") || cellport.second != "\\Y") { log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); return false; @@ -179,7 +179,7 @@ static void extract_fsm(RTLIL::Wire *wire) std::set<sig2driver_entry_t> cellport_list; sig2driver.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") continue; log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); @@ -223,7 +223,7 @@ static void extract_fsm(RTLIL::Wire *wire) cellport_list.clear(); sig2trigger.find(dff_out, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); RTLIL::SigSpec sig_b = assign_map(cell->get("\\B")); RTLIL::SigSpec sig_y = assign_map(cell->get("\\Y")); @@ -293,7 +293,7 @@ static void extract_fsm(RTLIL::Wire *wire) cellport_list.clear(); sig2driver.find(ctrl_out, cellport_list); for (auto &cellport : cellport_list) { - RTLIL::Cell *cell = module->cells.at(cellport.first); + RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec port_sig = assign_map(cell->get(cellport.second)); RTLIL::SigSpec unconn_sig = port_sig.extract(ctrl_out); RTLIL::Wire *unconn_wire = module->addWire(stringf("$fsm_unconnect$%s$%d", log_signal(unconn_sig), RTLIL::autoidx++), unconn_sig.size()); @@ -340,7 +340,7 @@ struct FsmExtractPass : public Pass { sig2driver.clear(); sig2trigger.clear(); - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) for (auto &conn_it : cell_it.second->connections()) { if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { RTLIL::SigSpec sig = conn_it.second; diff --git a/passes/fsm/fsm_info.cc b/passes/fsm/fsm_info.cc index f2d0c1a8..4526939c 100644 --- a/passes/fsm/fsm_info.cc +++ b/passes/fsm/fsm_info.cc @@ -45,7 +45,7 @@ struct FsmInfoPass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { log("\n"); log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str()); diff --git a/passes/fsm/fsm_map.cc b/passes/fsm/fsm_map.cc index 7ab15954..f6ef12a7 100644 --- a/passes/fsm/fsm_map.cc +++ b/passes/fsm/fsm_map.cc @@ -313,7 +313,7 @@ struct FsmMapPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> fsm_cells; - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_cells.push_back(cell_it.second); for (auto cell : fsm_cells) diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc index 1441378a..165b0974 100644 --- a/passes/fsm/fsm_opt.cc +++ b/passes/fsm/fsm_opt.cc @@ -290,7 +290,7 @@ struct FsmOptPass : public Pass { for (auto &mod_it : design->modules) { if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" and design->selected(mod_it.second, cell_it.second)) FsmData::optimize_fsm(cell_it.second, mod_it.second); } diff --git a/passes/fsm/fsm_recode.cc b/passes/fsm/fsm_recode.cc index b0228796..1b2eeb23 100644 --- a/passes/fsm/fsm_recode.cc +++ b/passes/fsm/fsm_recode.cc @@ -146,7 +146,7 @@ struct FsmRecodePass : public Pass { for (auto &mod_it : design->modules) if (design->selected(mod_it.second)) - for (auto &cell_it : mod_it.second->cells) + for (auto &cell_it : mod_it.second->cells_) if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, default_encoding); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index a266c344..550ec39f 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -38,7 +38,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell std::set<std::string> found_celltypes; for (auto i1 : design->modules) - for (auto i2 : i1.second->cells) + for (auto i2 : i1.second->cells_) { RTLIL::Cell *cell = i2.second; if (cell->type[0] == '$' || design->modules.count(cell->type) > 0) @@ -56,7 +56,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell log("Generate module for cell type %s:\n", celltype.c_str()); for (auto i1 : design->modules) - for (auto i2 : i1.second->cells) + for (auto i2 : i1.second->cells_) if (i2.second->type == celltype) { for (auto &conn : i2.second->connections()) { if (conn.first[0] != '$') @@ -137,7 +137,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla std::map<RTLIL::Cell*, std::pair<int, int>> array_cells; std::string filename; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; @@ -252,7 +252,7 @@ static void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*> &us log("Used module: %*s%s\n", indent, "", mod->name.c_str()); used.insert(mod); - for (auto &it : mod->cells) { + for (auto &it : mod->cells_) { if (design->modules.count(it.second->type) > 0) hierarchy_worker(design, used, design->modules[it.second->type], indent+4); } @@ -479,7 +479,7 @@ struct HierarchyPass : public Pass { std::vector<std::pair<RTLIL::Module*,RTLIL::Cell*>> pos_work; for (auto &mod_it : design->modules) - for (auto &cell_it : mod_it.second->cells) { + for (auto &cell_it : mod_it.second->cells_) { RTLIL::Cell *cell = cell_it.second; if (design->modules.count(cell->type) == 0) continue; diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 774aabae..37410275 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -87,7 +87,7 @@ struct SubmodWorker flag_signal(conn.second, true, true, true, false, false); } } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (submod.cells.count(cell) > 0) continue; @@ -215,7 +215,7 @@ struct SubmodWorker for (auto &it : module->wires_) it.second->attributes.erase("\\submod"); - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) { @@ -239,7 +239,7 @@ struct SubmodWorker } else { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (!design->selected(module, cell)) diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc index a8caf883..d5995ee0 100644 --- a/passes/memory/memory_collect.cc +++ b/passes/memory/memory_collect.cc @@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory) std::vector<RTLIL::Cell*> del_cells; std::vector<RTLIL::Cell*> memcells; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name) memcells.push_back(cell); diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc index b63b3aec..bb8b052d 100644 --- a/passes/memory/memory_dff.cc +++ b/passes/memory/memory_dff.cc @@ -38,7 +38,7 @@ static bool find_sig_before_dff(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLI if (bit.wire == NULL) continue; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; @@ -120,7 +120,7 @@ static void disconnect_dff(RTLIL::Module *module, RTLIL::SigSpec sig) RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff") { RTLIL::SigSpec new_q = cell->get("\\Q"); @@ -170,7 +170,7 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_wr_only) { - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { if (!design->selected(module, cell_it.second)) continue; if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool()) diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc index 4f166653..4bb0c8cc 100644 --- a/passes/memory/memory_map.cc +++ b/passes/memory/memory_map.cc @@ -295,7 +295,7 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell) static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector<RTLIL::Cell*> cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) if (it.second->type == "$mem" && design->selected(module, it.second)) cells.push_back(it.second); for (auto cell : cells) diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index 35a28d17..b25cf73a 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -143,7 +143,7 @@ struct MemoryShareWorker non_feedback_nets.insert(bits.begin(), bits.end()); } - for (auto cell_it : module->cells) + for (auto cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; bool ignore_data_port = false; @@ -650,7 +650,7 @@ struct MemoryShareWorker std::map<std::string, std::pair<std::vector<RTLIL::Cell*>, std::vector<RTLIL::Cell*>>> memindex; sigmap_xmux = sigmap; - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc index f0835076..48b83f5f 100644 --- a/passes/memory/memory_unpack.cc +++ b/passes/memory/memory_unpack.cc @@ -80,11 +80,11 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory) static void handle_module(RTLIL::Design *design, RTLIL::Module *module) { std::vector<RTLIL::IdString> memcells; - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second)) memcells.push_back(cell_it.first); for (auto &it : memcells) - handle_memory(module, module->cells.at(it)); + handle_memory(module, module->cells_.at(it)); } struct MemoryUnpackPass : public Pass { diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 9542e10d..4cc5fc89 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -38,7 +38,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose) std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> queue, unused; SigSet<RTLIL::Cell*> wire2driver; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; for (auto &it2 : cell->connections()) { if (!ct.cell_input(cell->type, it2.first)) { @@ -155,7 +155,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool SigPool connected_signals; if (!purge_mode) - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (ct_reg.cell_known(cell->type)) for (auto &it2 : cell->connections()) @@ -168,7 +168,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool SigMap assign_map(module); std::set<RTLIL::SigSpec> direct_sigs; std::set<RTLIL::Wire*> direct_wires; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; if (ct_all.cell_known(cell->type)) for (auto &it2 : cell->connections()) @@ -193,7 +193,7 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool SigPool used_signals; SigPool used_signals_nodrivers; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; for (auto &it2 : cell->connections_) { assign_map.apply(it2.second); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 290d4ffd..39e2254e 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -37,7 +37,7 @@ static void replace_undriven(RTLIL::Design *design, RTLIL::Module *module) SigPool used_signals; SigPool all_signals; - for (auto &it : module->cells) + for (auto &it : module->cells_) for (auto &conn : it.second->connections()) { if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) driven_signals.add(sigmap(conn.second)); @@ -199,8 +199,8 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo std::map<RTLIL::SigSpec, RTLIL::SigSpec> invert_map; std::vector<RTLIL::Cell*> cells; - cells.reserve(module->cells.size()); - for (auto &cell_it : module->cells) + cells.reserve(module->cells_.size()); + for (auto &cell_it : module->cells_) if (design->selected(module, cell_it.second)) { if ((cell_it.second->type == "$_INV_" || cell_it.second->type == "$not" || cell_it.second->type == "$logic_not") && cell_it.second->get("\\A").size() == 1 && cell_it.second->get("\\Y").size() == 1) diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 16dedef5..1d4916b5 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -83,7 +83,7 @@ struct OptMuxtreeWorker // .ctrl_sigs // .input_sigs // .const_activated - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" || cell->type == "$pmux" || cell->type == "$safe_pmux") diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc index 1f8648c4..d7de7235 100644 --- a/passes/opt/opt_reduce.cc +++ b/passes/opt/opt_reduce.cc @@ -254,14 +254,14 @@ struct OptReduceWorker did_something = true; SigPool mem_wren_sigs; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mem") mem_wren_sigs.add(assign_map(cell->get("\\WR_EN"))); if (cell->type == "$memwr") mem_wren_sigs.add(assign_map(cell->get("\\EN"))); } - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$dff" && mem_wren_sigs.check_any(assign_map(cell->get("\\Q")))) mem_wren_sigs.add(assign_map(cell->get("\\D"))); @@ -270,7 +270,7 @@ struct OptReduceWorker bool keep_expanding_mem_wren_sigs = true; while (keep_expanding_mem_wren_sigs) { keep_expanding_mem_wren_sigs = false; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$mux" && mem_wren_sigs.check_any(assign_map(cell->get("\\Y")))) { if (!mem_wren_sigs.check_all(assign_map(cell->get("\\A"))) || @@ -295,7 +295,7 @@ struct OptReduceWorker SigSet<RTLIL::Cell*> drivers; std::set<RTLIL::Cell*> cells; - for (auto &cell_it : module->cells) { + for (auto &cell_it : module->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type != type || !design->selected(module, cell)) continue; @@ -313,7 +313,7 @@ struct OptReduceWorker std::vector<RTLIL::Cell*> cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) if ((it.second->type == "$mux" || it.second->type == "$pmux" || it.second->type == "$safe_pmux") && design->selected(module, it.second)) cells.push_back(it.second); diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc index b26e8b37..14b734d7 100644 --- a/passes/opt/opt_rmdff.cc +++ b/passes/opt/opt_rmdff.cc @@ -179,7 +179,7 @@ struct OptRmdffPass : public Pass { mux_drivers.clear(); std::vector<std::string> dff_list; - for (auto &it : mod_it.second->cells) { + for (auto &it : mod_it.second->cells_) { if (it.second->type == "$mux" || it.second->type == "$pmux") { if (it.second->get("\\A").size() == it.second->get("\\B").size()) mux_drivers.insert(assign_map(it.second->get("\\Y")), it.second); @@ -202,8 +202,8 @@ struct OptRmdffPass : public Pass { } for (auto &id : dff_list) { - if (mod_it.second->cells.count(id) > 0 && - handle_dff(mod_it.second, mod_it.second->cells[id])) + if (mod_it.second->cells_.count(id) > 0 && + handle_dff(mod_it.second, mod_it.second->cells_[id])) total_count++; } } diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc index c91f037d..304ba9f8 100644 --- a/passes/opt/opt_share.cc +++ b/passes/opt/opt_share.cc @@ -248,8 +248,8 @@ struct OptShareWorker cell_hash_cache.clear(); #endif std::vector<RTLIL::Cell*> cells; - cells.reserve(module->cells.size()); - for (auto &it : module->cells) { + cells.reserve(module->cells_.size()); + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type) && design->selected(module, it.second)) cells.push_back(it.second); } diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index 565d86a7..63d04d35 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -33,7 +33,7 @@ static bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSp if (signal == ref) return true; - for (auto &cell_it : mod->cells) { + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (cell->type == "$reduce_or" && cell->get("\\Y") == signal) return check_signal(mod, cell->get("\\A"), ref, polarity); diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index d4ff2a86..45423326 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -147,7 +147,7 @@ struct VlogHammerReporter SatGen satgen(&ez, &sigmap); satgen.model_undef = model_undef; - for (auto &c : module->cells) + for (auto &c : module->cells_) if (!satgen.importCell(c.second)) log_error("Failed to import cell %s (type %s) to SAT database.\n", RTLIL::id2cstr(c.first), RTLIL::id2cstr(c.second->type)); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index c30e6e0c..24b812bb 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -82,7 +82,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu SigMap sigmap(module); SigPool dffsignals; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type) && it.second->has("\\Q")) dffsignals.add(sigmap(it.second->get("\\Q"))); } @@ -98,7 +98,7 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL: std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info; SigMap sigmap(module); - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (!design->selected(module, it.second)) continue; @@ -371,7 +371,7 @@ struct ExposePass : public Pass { shared_wires.insert(it.first); if (flag_evert) - for (auto &it : module->cells) + for (auto &it : module->cells_) if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second)) shared_cells.insert(it.first); @@ -409,16 +409,16 @@ struct ExposePass : public Pass { { RTLIL::Cell *cell; - if (module->cells.count(it) == 0) + if (module->cells_.count(it) == 0) goto delete_shared_cell; - cell = module->cells.at(it); + cell = module->cells_.at(it); if (!design->selected(module, cell)) goto delete_shared_cell; if (!consider_cell(design, dff_cells[module], cell)) goto delete_shared_cell; - if (!compare_cells(first_module->cells.at(it), cell)) + if (!compare_cells(first_module->cells_.at(it), cell)) goto delete_shared_cell; if (0) @@ -475,7 +475,7 @@ struct ExposePass : public Pass { if (flag_cut) { - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (!ct.cell_known(it.second->type)) continue; for (auto &conn : it.second->connections_) @@ -503,7 +503,7 @@ struct ExposePass : public Pass { RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); for (auto &cell_name : info.cells) { - RTLIL::Cell *cell = module->cells.at(cell_name); + RTLIL::Cell *cell = module->cells_.at(cell_name); std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->get("\\Q")).to_sigbit_vector(); for (auto &bit : cell_q_bits) if (wire_bits_set.count(bit)) @@ -571,7 +571,7 @@ struct ExposePass : public Pass { { std::vector<RTLIL::Cell*> delete_cells; - for (auto &it : module->cells) + for (auto &it : module->cells_) { if (flag_shared) { if (shared_cells.count(it.first) == 0) diff --git a/passes/sat/freduce.cc b/passes/sat/freduce.cc index 5d23318c..f8d5cf6c 100644 --- a/passes/sat/freduce.cc +++ b/passes/sat/freduce.cc @@ -607,7 +607,7 @@ struct FreduceWorker batches.push_back(sigmap(it.second).to_sigbit_set()); bits_full_total += it.second->width; } - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> inputs, outputs; for (auto &port : it.second->connections()) { diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 90c67116..3e1c7222 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -317,7 +317,7 @@ struct SatHelper } int import_cell_counter = 0; - for (auto &c : module->cells) + for (auto &c : module->cells_) if (design->selected(module, c.second)) { // log("Import cell: %s\n", RTLIL::id2cstr(c.first)); if (satgen.importCell(c.second, timestep)) { diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 0ee5af18..facacf19 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -61,7 +61,7 @@ struct ShareWorker queue_bits.insert(modwalker.signal_outputs.begin(), modwalker.signal_outputs.end()); - for (auto &it : module->cells) + for (auto &it : module->cells_) if (!fwd_ct.cell_known(it.second->type)) { std::set<RTLIL::SigBit> &bits = modwalker.cell_inputs[it.second]; queue_bits.insert(bits.begin(), bits.end()); @@ -101,7 +101,7 @@ struct ShareWorker void find_shareable_cells() { - for (auto &it : module->cells) + for (auto &it : module->cells_) { RTLIL::Cell *cell = it.second; diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc index eabc56bd..01284656 100644 --- a/passes/techmap/dfflibmap.cc +++ b/passes/techmap/dfflibmap.cc @@ -388,7 +388,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module) log("Mapping DFF cells in module `%s':\n", module->name.c_str()); std::vector<RTLIL::Cell*> cell_list; - for (auto &it : module->cells) { + for (auto &it : module->cells_) { if (design->selected(module, it.second) && cell_mappings.count(it.second->type) > 0) cell_list.push_back(it.second); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 813e0e3e..b66a11b8 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -182,7 +182,7 @@ namespace std::map<std::pair<RTLIL::Wire*, int>, int> sig_use_count; if (max_fanout > 0) - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (!sel || sel->selected(mod, cell)) @@ -196,7 +196,7 @@ namespace } // create graph nodes from cells - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) @@ -253,7 +253,7 @@ namespace } // mark external signals (used in non-selected cells) - for (auto &cell_it : mod->cells) + for (auto &cell_it : mod->cells_) { RTLIL::Cell *cell = cell_it.second; if (sel && !sel->selected(mod, cell)) diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 355c07c8..8c7f6423 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -439,7 +439,7 @@ struct SimplemapPass : public Pass { if (!design->selected(mod_it.second)) continue; std::vector<RTLIL::Cell*> delete_cells; - for (auto &cell_it : mod_it.second->cells) { + for (auto &cell_it : mod_it.second->cells_) { if (mappers.count(cell_it.second->type) == 0) continue; if (!design->selected(mod_it.second, cell_it.second)) diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 03aac669..86d9e73a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -116,7 +116,7 @@ struct TechmapWorker std::string orig_cell_name; if (!flatten_mode) - for (auto &it : tpl->cells) + for (auto &it : tpl->cells_) if (it.first == "\\_TECHMAP_REPLACE_") { orig_cell_name = cell->name; module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name); @@ -180,7 +180,7 @@ struct TechmapWorker } } - for (auto &it : tpl->cells) + for (auto &it : tpl->cells_) { RTLIL::IdString c_name = it.second->name; @@ -224,15 +224,15 @@ struct TechmapWorker std::vector<std::string> cell_names; SigMap sigmap(module); - for (auto &cell_it : module->cells) + for (auto &cell_it : module->cells_) cell_names.push_back(cell_it.first); for (auto &cell_name : cell_names) { - if (module->cells.count(cell_name) == 0) + if (module->cells_.count(cell_name) == 0) continue; - RTLIL::Cell *cell = module->cells[cell_name]; + RTLIL::Cell *cell = module->cells_[cell_name]; if (!design->selected(module, cell) || handled_cells.count(cell) > 0) continue; |