diff options
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/add.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_detect.cc | 2 | ||||
| -rw-r--r-- | passes/fsm/fsm_expand.cc | 16 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 2 | ||||
| -rw-r--r-- | passes/opt/opt_const.cc | 4 | ||||
| -rw-r--r-- | passes/sat/expose.cc | 4 |
6 files changed, 15 insertions, 15 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 1401193f..f94ea639 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -75,7 +75,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n continue; if (mod->get_bool_attribute("\\blackbox")) continue; - if (it.second->connections().count(name) > 0) + if (it.second->has(name)) continue; it.second->set(name, wire); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index be851afa..55fe336f 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -80,7 +80,7 @@ static bool check_state_users(RTLIL::SigSpec sig) continue; if (cellport.second != "\\A" && cellport.second != "\\B") return false; - if (cell->connections().count("\\A") == 0 || cell->connections().count("\\B") == 0 || cell->connections().count("\\Y") == 0) + if (!cell->has("\\A") || !cell->has("\\B") || !cell->has("\\Y")) return false; for (auto &port_it : cell->connections()) if (port_it.first != "\\A" && port_it.first != "\\B" && port_it.first != "\\Y") diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index ed80d7c3..186ea2fd 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -47,13 +47,13 @@ struct FsmExpand return true; RTLIL::SigSpec new_signals; - if (cell->connections().count("\\A") > 0) + if (cell->has("\\A")) new_signals.append(assign_map(cell->get("\\A"))); - if (cell->connections().count("\\B") > 0) + if (cell->has("\\B")) new_signals.append(assign_map(cell->get("\\B"))); - if (cell->connections().count("\\S") > 0) + if (cell->has("\\S")) new_signals.append(assign_map(cell->get("\\S"))); - if (cell->connections().count("\\Y") > 0) + if (cell->has("\\Y")) new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); @@ -65,7 +65,7 @@ struct FsmExpand if (new_signals.size() > 3) return false; - if (cell->connections().count("\\Y") > 0) { + if (cell->has("\\Y")) { new_signals.append(assign_map(cell->get("\\Y"))); new_signals.sort_and_unify(); new_signals.remove_const(); @@ -148,11 +148,11 @@ struct FsmExpand for (int i = 0; i < (1 << input_sig.size()); i++) { RTLIL::Const in_val(i, input_sig.size()); RTLIL::SigSpec A, B, S; - if (cell->connections().count("\\A") > 0) + if (cell->has("\\A")) A = assign_map(cell->get("\\A")); - if (cell->connections().count("\\B") > 0) + if (cell->has("\\B")) B = assign_map(cell->get("\\B")); - if (cell->connections().count("\\S") > 0) + if (cell->has("\\S")) S = assign_map(cell->get("\\S")); A.replace(input_sig, RTLIL::SigSpec(in_val)); B.replace(input_sig, RTLIL::SigSpec(in_val)); diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index e89bba89..ff3ac760 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -350,7 +350,7 @@ struct FsmExtractPass : public Pass { assign_map.apply(sig); sig2driver.insert(sig, sig2driver_entry_t(cell_it.first, conn_it.first)); } - if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->connections().count("\\Y") > 0 && + if (ct.cell_input(cell_it.second->type, conn_it.first) && cell_it.second->has("\\Y") && cell_it.second->get("\\Y").size() == 1 && (conn_it.first == "\\A" || conn_it.first == "\\B")) { RTLIL::SigSpec sig = conn_it.second; assign_map.apply(sig); diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index e5288231..000a9ec2 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -88,7 +88,7 @@ static void replace_cell(RTLIL::Module *module, RTLIL::Cell *cell, std::string i static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap) { - std::string b_name = cell->connections().count("\\B") ? "\\B" : "\\A"; + std::string b_name = cell->has("\\B") ? "\\B" : "\\A"; bool a_signed = cell->parameters.at("\\A_SIGNED").as_bool(); bool b_signed = cell->parameters.at(b_name + "_SIGNED").as_bool(); @@ -321,7 +321,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow") { RTLIL::SigSpec sig_a = assign_map(cell->get("\\A")); - RTLIL::SigSpec sig_b = cell->connections().count("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); + RTLIL::SigSpec sig_b = cell->has("\\B") ? assign_map(cell->get("\\B")) : RTLIL::SigSpec(); if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") sig_a = RTLIL::SigSpec(); diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc index a84faf79..198f8347 100644 --- a/passes/sat/expose.cc +++ b/passes/sat/expose.cc @@ -83,7 +83,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu SigPool dffsignals; for (auto &it : module->cells) { - if (ct.cell_known(it.second->type) && it.second->connections().count("\\Q")) + if (ct.cell_known(it.second->type) && it.second->has("\\Q")) dffsignals.add(sigmap(it.second->get("\\Q"))); } @@ -628,7 +628,7 @@ struct ExposePass : public Pass { log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type)); RTLIL::SigSpec sig; - if (cell->connections().count(p->name) != 0) + if (cell->has(p->name)) sig = cell->connections().at(p->name); sig.extend(w->width); if (w->port_input) |